公开(公告)号：US06324634B1

公开(公告)日：2001-11-27

申请号：US09693678

申请日：2000-10-19

Applicant: Shinichi Yoshioka ,  Shumpei Kawasaki

Inventor： Shinichi Yoshioka ,  Shumpei Kawasaki

IPC: G06F1200

CPC classification number: G06F12/1063 ,  G06F2212/652 ,  Y02D10/13

Abstract: Physical page information PA(a) corresponding to logical page information VA(a) as a cache tag address is retained in a logical cache memory 10 and in the event of a cache miss when a shared area is accessed, the physical page information PA (a) retained in the cache memory is compared with physical page information PA (b) resulting from the translation of a search address by TLB. When the result of the comparison is proved to be conformity, the cache entry is processes as a cache hit, so that the problem of a synonym arising from a case where the same physical address is assigned to different logical addresses is solved in such a manner that the number of times access is provided to TLB is halved as compared with the conventional arrangement.

Abstract translation: 对应于作为高速缓存标签地址的逻辑页面信息VA（a）的物理页面信息PA（a）被保留在逻辑高速缓存存储器10中，并且在访问共享区域时出现高速缓存未命中的情况下，物理页面信息PA a）保留在高速缓冲存储器中的物理页面信息PA（b）与通过TLB翻译搜索地址而产生的物理页面信息PA（b）进行比较。 当比较结果被证明是一致的时候，高速缓存条目被作为高速缓存命中处理，从而以相同的物理地址被分配给不同的逻辑地址的情况产生同义词的问题 与常规布置相比，访问被提供给TLB的次数减半。

公开(公告)号：US06266755B1

公开(公告)日：2001-07-24

申请号：US08772233

申请日：1996-12-23

Applicant: Kenneth C. Yeager

Inventor： Kenneth C. Yeager

IPC: G06F934

CPC classification number: G11C29/88 ,  G06F11/004 ,  G06F12/1027 ,  G06F2212/1032 ,  G06F2212/652

Abstract: A translation lookaside buffer for detecting and preventing conflicting virtual addresses from being stored therein is disclosed. Each entry in the buffer is associated with a switch which can be set and reset to enable and disable, respectively, a buffer entry. A switch associated with an existing entry will be reset if such entry conflicts with a new buffer entry.

Abstract translation: 公开了用于检测和防止存在冲突的虚拟地址的翻译后备缓冲器。 缓冲器中的每个条目与可以被设置和复位以分别启用和禁用缓冲器条目的开关相关联。 如果这样的条目与新的缓冲区条目冲突，则与现有条目关联的切换将被重置。

公开(公告)号：US06205530B1

公开(公告)日：2001-03-20

申请号：US09073968

申请日：1998-05-07

Applicant: Hoai Sig Kang

Inventor： Hoai Sig Kang

IPC: G06F1200

CPC classification number: G06F12/1027 ,  G06F2212/652

Abstract: An address translation unit for supporting multiple page modes, with each page mode having a different page size. The address translation unit includes a tag interface unit for outputting effective tag data in response to a page mode select signal, a tag memory for storing tag data and for comparing the effective tag data with previously stored tag data to generate a comparison signal in response to a word signal and a write control signal, a data interface unit for outputting effective physical data in response to the page mode select signal, a data memory for storing effective physical data from the data interface unit and for outputting a converted physical address in response to the word signal, the write control signal and the comparison signal, a decoder interface unit for receiving a part of a linear address in response to a page mode signal and for outputting the part of the linear address as an entry index signal, and a decoding unit for decoding the part of the linear address and outputting the word signal selecting an entry to the tag memory and the data memory in response to the entry index signal, the write control signal and a write way signal.

Abstract translation: 一种用于支持多页模式的地址转换单元，每个页面模式具有不同的页面大小。 地址转换单元包括：标签接口单元，用于响应于页面模式选择信号输出有效的标签数据;标签存储器，用于存储标签数据，并用于将有效标签数据与先前存储的标签数据进行比较，以响应于 字信号和写控制信号，用于响应于页模式选择信号输出有效物理数据的数据接口单元，用于存储来自数据接口单元的有效物理数据的数据存储器，并响应于 字信号，写控制信号和比较信号，解码器接口单元，用于响应于页模式信号接收线性地址的一部分，并输出该部分线性地址作为入口索引信号，以及解码 单元，用于对所述线性地址的一部分进行解码，并且响应于所述条目输出将所述字信号选择到所述标签存储器和所述数据存储器的条目 索引信号，写入控制信号和写入方式信号。

公开(公告)号：US6026476A

公开(公告)日：2000-02-15

申请号：US907280

申请日：1997-08-06

Applicant: Eitan E. Rosen

Inventor： Eitan E. Rosen

IPC: G06F12/10 ,  G06F12/00

CPC classification number: G06F12/1027 ,  G06F2212/652

Abstract: A fast, fully associative translation lookaside buffer (TLB) with the ability to store and manage information pertaining to at least two different page sizes is disclosed. The TLB utilizes a tag array with tag lines and a data array with corresponding data lines. Within the tag array, each tag line incorporates a control cell which selectively enables or disables comparisons of tag bits to corresponding bits from an input address to the TLB. Within the data array, each data line incorporates control cells and multiplexing data cells to selectively determine whether bits in the physical address output of the TLB will be the derived from of the contents of the multiplexing data cells or bits from the input address. The use of control cells in the tag array and control cells and multiplexing data cells in the data array thereby provides for the ability to store and manage information pertaining to at least two different page sizes in a single TLB.

Abstract translation: 公开了一种快速，完全关联的翻译后备缓冲器（TLB），具有存储和管理与至少两个不同页面大小有关的信息的能力。 TLB利用具有标签行的标签阵列和具有相应数据线的数据阵列。 在标签阵列内，每个标签行包含一个控制单元，该控制单元有选择地启用或禁止标签位与从输入地址到TLB的相应位的比较。 在数据阵列内，每个数据线合并了控制单元和多路复用数据单元，以选择性地确定TLB的物理地址输出中的位是否来自多路复用数据单元的内容或来自输入地址的位。 在标签阵列和控制单元中使用控制单元以及数据阵列中的多路复用数据单元由此提供在单个TLB中存储和管理与至少两个不同页面尺寸有关的信息的能力。

公开(公告)号：US6014732A

公开(公告)日：2000-01-11

申请号：US955821

申请日：1997-10-22

Applicant: Samuel D. Naffziger

Inventor： Samuel D. Naffziger

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1045 ,  G06F12/0864 ,  G06F12/1054 ,  G06F2212/652

Abstract: A cache with a translation lookaside buffer (TLB) that eliminates the need for retrieval of a physical address tag from the TLB when accessing the cache. The TLB includes two content addressable memories (CAM's). For each new cache line, in the tag portion of the cache, instead of storing physical tags, the cache stores vectors called physical hit vectors. Physical hit vectors are generated by a first TLB CAM. Each physical hit vector indicates all locations in the first TLB CAM containing the physical tag of the cache line. For a cache access, a second TLB CAM receives a virtual tag and generates a vector called a virtual hit vector. The virtual hit vector indicates the location in the second TLB CAM of the corresponding virtual tag. Then, instead of retrieving and comparing physical tags, the cache compares a virtual hit vector to a set of physical hit vectors without having to retrieve a physical tag. As a result, one operation is eliminated from a time critical path, reducing the access time. For caches having variable page sizes, an additional CAM structure stores page offset bits and corresponding bit masks from the operating system. Page offset bits are then used to further qualify comparison of virtual hit vectors and physical hit vectors.

Abstract translation: 具有翻译后备缓冲器（TLB）的缓存，消除了在访问高速缓存时从TLB检索物理地址标签的需要。 TLB包括两个内容可寻址存储器（CAM）。 对于每个新的高速缓存行，在缓存的标签部分中，高速缓存存储物理标记，而不是存储物理标记，存储称为物理命中向量的向量。 物理撞击矢量由第一TLB CAM产生。 每个物理命中矢量指示包含高速缓存行的物理标记的第一TLB CAM中的所有位置。 对于高速缓存访​​问，第二TLB CAM接收虚拟标签并生成称为虚拟命中向量的向量。 虚拟命中向量表示相应虚拟标签的第二TLB CAM中的位置。 然后，高速缓存将虚拟命中向量与一组物理命中矢量进行比较，而不用检索和比较物理标签，而不用检索物理标签。 因此，从时间关键路径消除一个操作，减少访问时间。 对于具有可变页面大小的高速缓存，附加的CAM结构存储来自操作系统的页偏移位和对应的位掩码。 然后使用页面偏移位来进一步限定虚拟命中矢量和物理命中矢量的比较。

公开(公告)号：US5956756A

公开(公告)日：1999-09-21

申请号：US874201

申请日：1997-06-06

Applicant: Yousef A. Khalidi ,  Glen R. Anderson ,  Stephen A. Chessin ,  Shing Ip Kong ,  Charles E. Narad ,  Madhusudhan Talluri

Inventor： Yousef A. Khalidi ,  Glen R. Anderson ,  Stephen A. Chessin ,  Shing Ip Kong ,  Charles E. Narad ,  Madhusudhan Talluri

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/652

Abstract: A method and apparatus for translating a virtual address to a physical address. A virtual address to be translated has a virtual page offset and a virtual page number. The virtual address to be translated addresses a page of memory. The size of this page is unknown. There are L different possible page sizes where L is a positive integer greater than one. Each of the L different page sizes is selected to be a test page size and a test is performed. During the test, a pointer into a translation storage buffer is calculated. The pointer is calculated from the virtual address to be translated by assuming that the virtual address to be translated corresponds to a mapping of the test page size. The pointer points to a candidate translation table entry of the translation storage buffer. The candidate translation table entry has a candidate tag and candidate data. The candidate tag identifies a particular virtual address and the candidate data identifies a particular physical address corresponding to the particular virtual address. A virtual address target tag is extracted from the virtual address to be translated. The virtual address target tag is calculated by assuming that the virtual address to be translated corresponds to a mapping of the test page size. The target tag and the candidate tag are then compared. If the target tag matches the candidate tag, the candidate data is provided as the physical address translation corresponding to the virtual address to be translated.

Abstract translation: 一种用于将虚拟地址翻译成物理地址的方法和装置。 要翻译的虚拟地址具有虚拟页面偏移量和虚拟页面编号。 要转换的虚拟地址可寻址内存页面。 此页面的大小是未知的。 有L个不同的可能的页面大小，其中L是大于1的正整数。 选择L个不同页面大小中的每一个作为测试页面大小并执行测试。 在测试期间，计算指向转换存储缓冲区的指针。 通过假设要转换的虚拟地址对应于测试页大小的映射，从要转换的虚拟地址计算指针。 指针指向翻译存储缓冲器的候选翻译表条目。 候选翻译表条目具有候选标签和候选数据。 候选标签识别特定的虚拟地址，并且候选数据标识对应于特定虚拟地址的特定物理地址。 从要翻译的虚拟地址中提取虚拟地址目标标签。 通过假设要转换的虚拟地址对应于测试页大小的映射来计算虚拟地址目标标签。 然后比较目标标签和候选标签。 如果目标标签与候选标签匹配，则将候选数据提供为与要翻译的虚拟地址相对应的物理地址转换。

公开(公告)号：US5907867A

公开(公告)日：1999-05-25

申请号：US657231

申请日：1996-06-03

Applicant: Toshinobu Shinbo ,  Suguru Tachibana ,  Susumu Narita ,  Shinichi Yoshioka ,  Koichiro Ishibashi ,  Hisayuki Higuchi ,  Yoshinobu Nakagome ,  Ikuya Kawasaki ,  Saneaki Tamaki

Inventor： Toshinobu Shinbo ,  Suguru Tachibana ,  Susumu Narita ,  Shinichi Yoshioka ,  Koichiro Ishibashi ,  Hisayuki Higuchi ,  Yoshinobu Nakagome ,  Ikuya Kawasaki ,  Saneaki Tamaki

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/652 ,  Y02B60/1225

Abstract: A semiconductor integrated circuit device such as a data processing device having a set-associative translation look-aside buffer (TLB). A plurality of address arrays each have a second field for storing the value representing a page size. The values read from the second fields are used to change the range of address comparison by comparators. A plurality of data arrays each have a second field for storing a bit position address designating either an intra-page address or a page number following a page size change. The values read from the second fields of the address arrays are used as the basis for second selectors to select either an address in a predetermined location of an externally input virtual address or the address read from each of the second fields of the data arrays. The selected address is output as a physical address.

Abstract translation: 一种半导体集成电路装置，例如具有集相关翻译后备缓冲器（TLB）的数据处理装置。 多个地址阵列各自具有用于存储表示页面大小的值的第二字段。 从第二个字段读取的值用于通过比较器更改地址比较范围。 多个数据阵列各自具有用于存储指定页面大小改变之后的页内地址或页码的位位置地址的第二字段。 从地址阵列的第二个字段读取的值被用作第二选择器选择外部输入的虚拟地址的预定位置的地址或从数据阵列的每个第二场读取的地址的基础。 所选地址作为物理地址输出。

公开(公告)号：US5890201A

公开(公告)日：1999-03-30

申请号：US886761

申请日：1997-07-01

Applicant: Edward J. McLellan ,  Bruce A. Gieseke

Inventor： Edward J. McLellan ,  Bruce A. Gieseke

IPC: G06F12/10 ,  G11C15/04 ,  G06F12/00 ,  G11C15/00

CPC classification number: G06F12/1027 ,  G11C15/04 ,  G06F2212/652

Abstract: A method of accessing a content addressable memory storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state, is disclosed. The stored information is compared with a one bit signal. A match is indicated when the one bit signal represents a logic zero and the stored information represents the don't care state, or when the one bit signal represents a logic one and the stored information represents a don't care state. An absence of a match is indicated when the one bit signal represents a logic zero and the stored information represents an invalid state, or when the one bit signal represents a logic one and the stored information represents the invalid state. The content addressable memory is especially adapted for use in a translation buffer providing variable page granularity. The don't care state permits multiple virtual page numbers to match a single entry storing information for multiple physical pages. The invalid state eliminates the need for a dedicated valid bit in each entry.

Abstract translation: 公开了存储存储表示无效状态，逻辑零状态，逻辑1状态或无关状态的两位信息的内容可寻址存储器的方法。 存储的信息与一位信号进行比较。 当一位信号表示逻辑0并且存储的信息表示无关状态时，或者当一位信号表示逻辑1并且存储的信息表示无关状态时，指示匹配。 当一位信号表示逻辑0并且存储的信息表示无效状态时，或者当一位信号表示逻辑1并且存储的信息表示无效状态时，指示不存在匹配。 内容可寻址存储器特别适用于提供可变页面粒度的翻译缓冲器。 无关状态允许多个虚拟页码匹配存储多个物理页面的信息的单个条目。 无效状态消除了对每个条目中专用有效位的需要。

公开(公告)号：US5765201A

公开(公告)日：1998-06-09

申请号：US509486

申请日：1995-07-31

Applicant: Mark Gregory Manges ,  Lynn K. Chung ,  Shiun Lee ,  Arlys Jean Leitzen ,  Edwin Charles Grazier ,  Michael Joseph Corrigan ,  Mark Philip Piazza

Inventor： Mark Gregory Manges ,  Lynn K. Chung ,  Shiun Lee ,  Arlys Jean Leitzen ,  Edwin Charles Grazier ,  Michael Joseph Corrigan ,  Mark Philip Piazza

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/02

CPC classification number: G06F3/0607 ,  G06F12/10 ,  G06F3/0638 ,  G06F3/0676 ,  G06F2212/652

Abstract: When a computer system is upgraded, such as by adding a more advanced processor chip and/or a new operating system, a different page size may be employed. The page size is altered for data previously stored in a storage medium such as a hard disk in the computer system, without removing all of the data from the medium and rewriting it. Data is stored in the medium in blocks or sectors which have headers defining the block. Also, tables define memory objects and segments, and locate virtual memory addresses in physical memory. The headers and/or tables can be changed without rewriting all of the data in the sectors or pages in physical memory, so the page size is changed to accommodate the new system components, without excessive burden on system hardware or undue expenditure of time. In an example, in changing from a CISC processor with a 512-byte page size to a RISC system with a 4K-byte page size, the segments are changed to always be of a size of an integral multiple of 4K, and "extents" or subdivisions within a segment are changed to be multiples of 4K. Any excess space generated by these changes is zeroed. After alteration, the media (such as disks) can be accessed by either the CISC system or the new upgraded RISC system.

Abstract translation: 当升级计算机系统时，例如通过添加更先进的处理器芯片和/或新的操作系统，可以采用不同的页面大小。 对于先前存储在诸如计算机系统中的硬盘的存储介质中的数据，页面大小被改变，而不从介质中移除所有数据并重写它。 数据被存储在具有定义块的头部的块或扇区中的介质中。 此外，表定义内存对象和段，并在物理内存中定位虚拟内存地址。 可以改变报头和/或表，而无需重写物理存储器中的扇区或页面中的所有数据，因此页面大小被改变以适应新的系统组件，而不会对系统硬件造成过度的负担或不适当的时间支出。 在一个例子中，在从具有512字节页面大小的CISC处理器更改为具有4K字节页面大小的RISC系统时，段被改变为总是4K的整数倍的大小，并且“范围” 或分段内的细分被改变为4K的倍数。 由这些更改生成的任何多余的空间归零。 更改后，可以通过CISC系统或新升级的RISC系统访问介质（如磁盘）。

公开(公告)号：US5717885A

公开(公告)日：1998-02-10

申请号：US741749

申请日：1996-11-05

Applicant: Rajendra Kumar ,  Paul G. Emerson

Inventor： Rajendra Kumar ,  Paul G. Emerson

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/652

Abstract: A translation look-aside buffer (TLB) for translating a variable page size virtual page number to a physical page number. The TLB partitions the virtual page number into an upper portion and a lower portion. The upper portion is always compared to an upper virtual page number entry in a first content addressable memory while only certain bits of lower portion are selectively compared to a corresponding number of bits in a lower virtual page number entry in a second content addressable memory. The number of bits compared in the second content addressable memory is determined by the specified size of the physical page. The TLB includes a page size memory having a plurality of page size entries wherein the certain number of bits for each of the lower virtual page entries is specified by a corresponding page size entry. Associated with each bit in the lower virtual page number entries is an enable transistor for selectively enabling the comparison of that bit in the lower virtual page number entry. The enable gate includes a control input coupled to a corresponding bit in a corresponding page size entry, the enable transistor selectively enabling the single bit comparison when the corresponding bit in the page size entry is set to an enable state and selectively disabling the comparison when the corresponding bit in the page size entry is set to a disable state.

Abstract translation: 用于将可变页大小的虚拟页号翻译成物理页号的翻译后备缓冲器（TLB）。 TLB将虚拟页码分成上部和下部。 上部部分总是与第一内容可寻址存储器中的上虚拟页号码条目进行比较，而仅将下部分的某些比特选择性地与第二内容可寻址存储器中的较低虚拟页号码条目中的相应位数比较。 在第二内容可寻址存储器中比较的比特数由物理页面的指定大小确定。 TLB包括具有多个页面大小条目的页面大小存储器，其中每个较低虚拟页面条目的特定数量的位由相应的页面大小条目指定。 与较低虚拟页号码条目中的每个位相关联的是使能晶体管，用于选择性地启用较低虚拟页码条目中该位的比较。 使能栅极包括耦合到相应页面大小条目中的对应位的控制输入，当页面大小条目中的相应位被设置为使能状态时，使能晶体管有选择地启用单个位比较，并且当 页面大小条目中的相应位被设置为禁用状态。