公开(公告)号：US20100031099A1

公开(公告)日：2010-02-04

申请号：US12511957

申请日：2009-07-29

申请人： Gary L. Swoboda

发明人： Gary L. Swoboda

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/3177 ,  G01R31/31701 ,  G01R31/31713 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318533 ,  G01R31/318538 ,  G01R31/318544 ,  G06F11/22 ,  G06F11/267 ,  G06F11/27 ,  G06F11/36 ,  G06F11/3656 ,  G06F2201/88 ,  H04L43/50

摘要： Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

摘要翻译： 可以通过驱动数据输入信号上的低逻辑值和扫描拓扑的数据输出信号来执行具有与扫描拓扑结合的多个分量的目标系统的拓扑发现。 对多个分量中的每一个的输入数据值和输出数据值进行采样和记录。 然后通过扫描路径扫描低逻辑值，并记录在每个组件上。 可以基于记录的数据值和记录的扫描值来确定扫描拓扑。

公开(公告)号：US07631233B2

公开(公告)日：2009-12-08

申请号：US11868509

申请日：2007-10-07

申请人： Michael C. Parris ,  Oscar Frederick Jones, Jr.

发明人： Michael C. Parris ,  Oscar Frederick Jones, Jr.

IPC分类号： G11C29/00 ,  H04L1/00

CPC分类号： G01R31/31713 ,  G11C29/10 ,  G11C29/56 ,  G11C2029/0409

摘要： A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.

摘要翻译： 一种用于集成电路存储器测试的数据反转寄存器技术，其中数据输入信号以预定模式选择性地反转，以最大化在测试期间识别故障的可能性。 根据本发明的技术，在预定的输入/输出（I / O））数据输入可以被反转以创建对于I / O电路是“最坏情况”的期望的测试图案（诸如数据条纹），或者 列条纹是存储器阵列的“最坏情况”。 根据本发明的技术的电路然后匹配数据输出路径的模式，反转适当的数据输出以获得预期的测试器数据。 这样，测试模式对任何记忆测试仪都是透明的。

公开(公告)号：US07617430B2

公开(公告)日：2009-11-10

申请号：US11938923

申请日：2007-11-13

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G01R31/28

CPC分类号： G01R31/3172 ,  G01R31/31701 ,  G01R31/31705 ,  G01R31/31712 ,  G01R31/31713 ,  G01R31/31722 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318364 ,  G01R31/318555 ,  G01R31/318558 ,  G06F11/267

摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

摘要翻译： 本公开描述了可以在集成电路中的集成电路或嵌入式核心上使用的减少的引脚总线。 总线可用于串行访问电路，其中IC或引脚上的引脚的可用性受限制。 总线可用于各种串行通信操作，例如但不限于IC或核心设计的串行通信相关测试，仿真，调试和/或跟踪操作。 本公开的其他方面包括使用减少的针脚总线用于仿真，调试和跟踪操作以及功能操作。

公开(公告)号：US20090146756A1

公开(公告)日：2009-06-11

申请号：US12364296

申请日：2009-02-02

申请人： Hiroki FUJISAWA

发明人： Hiroki FUJISAWA

IPC分类号： H03H7/38

CPC分类号： H03H11/28 ,  G01R31/31713 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  H03K19/0005

摘要： To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.

摘要翻译： 减少校准输出电路所需的电路规模，并减少校准操作所需的时间。 本发明包括连接到数据引脚的第一输出缓冲器和第二输出缓冲器以及连接到校准引脚的校准电路。 第一输出缓冲器和第二输出缓冲器包括多个单元缓冲器。 单元缓冲器具有相互相同的电路结构。 利用这种布置，基于使用校准电路的校准操作，可以将第一输出缓冲器和第二输出缓冲器的阻抗设置为共同的。 因此，可以减少校准操作所需的电路规模和校准操作所需的时间。

公开(公告)号：US07495453B2

公开(公告)日：2009-02-24

申请号：US11783787

申请日：2007-04-12

申请人： Hiroki Fujisawa

发明人： Hiroki Fujisawa

IPC分类号： G01R35/00 ,  G01R31/26

CPC分类号： H03H11/28 ,  G01R31/31713 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  H03K19/0005

摘要： To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.

摘要翻译： 减少校准输出电路所需的电路规模，并减少校准操作所需的时间。 本发明包括连接到数据引脚的第一输出缓冲器和第二输出缓冲器以及连接到校准引脚的校准电路。 第一输出缓冲器和第二输出缓冲器包括多个单元缓冲器。 单元缓冲器具有相互相同的电路结构。 利用这种布置，基于使用校准电路的校准操作，可以将第一输出缓冲器和第二输出缓冲器的阻抗设置为共同的。 因此，可以减少校准操作所需的电路规模和校准操作所需的时间。

公开(公告)号：US07493536B2

公开(公告)日：2009-02-17

申请号：US11460515

申请日：2006-07-27

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G01R31/28

CPC分类号： H03K19/173 ,  G01R31/31713 ,  G01R31/31715 ,  G01R31/318572

摘要： An electronic integrated circuit includes a signal path connected between the functional logic and an external input terminal, which signal path includes a memory circuit. The memory circuit is coupled to the input terminal and is selectively operable to detect and resolve voltage contention at the input terminal, and is also selectively operable to isolate itself from voltages at the input terminal. The memory circuit has two data inputs, one from the input terminal and the other from a serial data path. The memory circuit has two control inputs, one to a first switch between the input terminal and an input buffer and the other to a second switch between the serial data path and the input buffer.

摘要翻译： 电子集成电路包括连接在功能逻辑和外部输入端之间的信号路径，该信号路径包括存储器电路。 存储器电路耦合到输入端子并且可选择性地操作以检测和解决输入端子处的电压争用，并且还可以选择性地操作以将其自身与输入端子处的电压隔离。 存储器电路具有两个数据输入，一个来自输入端，另一个来自串行数据通路。 存储器电路具有两个控制输入，一个输入端与一个输入缓冲器之间的第一个开关，另一个连接到串行数据通道和输入缓冲器之间的第二个开关。

公开(公告)号：US20080276029A1

公开(公告)日：2008-11-06

申请号：US11743720

申请日：2007-05-03

申请人： Ryan S. Haraden

发明人： Ryan S. Haraden

IPC分类号： G06F13/14

CPC分类号： G01R31/318519 ,  G01R31/31713

摘要： Flow of commands from logic under test, such as an FPGA, to a receiving component, such as a component in a PCIe hierarchy, is managed. A rate at which flow control signals are received by the logic under test from the receiving component is determined, the flow control signals indicating that there is space available in a buffer in the receiving component for receiving commands. The determined rate of receipt of the flow control signals is used for managing flow of commands from the logic under test to the receiving component without waiting for actual processing of flow control signals by the logic under test.

摘要翻译： 管理从诸如FPGA的被测逻辑到接收组件（诸如PCIe层次结构中的组件）的命令流程。 由接收组件确定流量控制信号被待测逻辑接收的速率，指示在接收组件中用于接收命令的缓冲器中有可用空间的流控制信号。 确定的流量控制信号的接收速率用于管理从被测逻辑到接收组件的命令流程，而不用等待被测逻辑的流量控制信号的实际处理。

公开(公告)号：US20080150608A1

公开(公告)日：2008-06-26

申请号：US11953739

申请日：2007-12-10

申请人： Marco Schreiter

发明人： Marco Schreiter

IPC分类号： H03K17/687

CPC分类号： H03K17/005 ,  G01R31/3163 ,  G01R31/31713 ,  H03K17/063 ,  H03K17/162 ,  H03K17/6872 ,  H03K17/6874 ,  H03K2017/066

摘要： An integrated semiconductor circuit is provided with a connection node, which is provided for decoupling electric signals, and with a plurality of electric signal lines, which are formed to provide in-circuit signals, particularly test signals, to the connection node. An in-circuit release device, which can be switched between a release state to release the signal line and a blocking state to block the signal line, is looped in the signal lines. The release device has switching means, which are formed in such a way that the blocking state for the signal line is assured irrespective of a signal or test signal electric potential applied to the signal line. The release device furthermore, has control means, which are provided for controlling the switching means. The control means can be formed in such a way that a cross-current-free release of the specific signal line is assured.

摘要翻译： 集成半导体电路设置有用于去耦电信号的连接节点，以及多个电信号线，其形成为向连接节点提供特别是测试信号的电路内信号。 可以在信号线路中环绕可以在释放信号线的释放状态和阻塞信号之间切换的在线释放装置。 释放装置具有切换装置，其形成为使得信号线的阻挡状态不受施加到信号线的信号或测试信号电位的影响而被确定。 此外，释放装置具有用于控制开关装置的控制装置。 控制装置可以形成为确保特定信号线的无交叉电流释放。

公开(公告)号：US20070294605A1

公开(公告)日：2007-12-20

申请号：US11803853

申请日：2007-05-15

申请人： Reiner Bidenbach ,  Joerg Franke ,  Joachim Ritter ,  Christian Jung

发明人： Reiner Bidenbach ,  Joerg Franke ,  Joachim Ritter ,  Christian Jung

IPC分类号： G01R31/28

CPC分类号： G01R31/31713 ,  G01R31/2844 ,  G01R31/2884

摘要： The invention relates to a circuit configuration with a serial test interface (TIF) to control a test operation mode, a freely programmable digital processor (CPU), a housing (G) for the accommodation of a test interface (TIF) and the processor (CPU) with terminals or connectors (C0, C1) for data and/or signal exchange with external components and setups. At one of the terminals (C1), a modulated supply voltage (VDD) can be received the transfer of data (d) and or a clock (T) by using at least two voltage levels (V2, V3) that can be controlled and which are different from a supply voltage level (V1) that is designed to feed the circuitry with a supply operating voltage. Furthermore, the invention relates to a serial test operation method for such a circuit configuration.

摘要翻译： 本发明涉及具有用于控制测试操作模式的串行测试接口（TIF）的电路配置，可自由编程的数字处理器（CPU），用于容纳测试接口（TIF）和处理器（TIF）的外壳 CPU），带有端子或连接器（C 0，C 1），用于与外部组件和设置进行数据和/或信号交换。 在其中一个端子（C 1）中，可以通过使用至少两个电压电平（V 2，V 3）来接收调制电源电压（VDD），数据传输（d）和/或时钟（T） 被控制，并且不同于被设计为将电路馈送到电源工作电压的电源电压电平（V 1）。 此外，本发明涉及一种用于这种电路配置的串行测试操作方法。

公开(公告)号：US20070290676A1

公开(公告)日：2007-12-20

申请号：US11846446

申请日：2007-08-28

申请人： Charles Miller

发明人： Charles Miller

IPC分类号： G01R1/06

CPC分类号： G01R31/2889 ,  G01R31/31713

摘要： An emitter follower or source follower transistor is provided in the channel of a wafer test system between a DUT and a test system controller to enable a low power DUT to drive a test system channel. A bypass resistor is included between the base and emitter of the emitter follower transistor to enable bi-directional signals to be provided between the DUT channel and test system controller, as well as to enable parametric tests to be performed. The emitter follower transistor and bypass resistor can be provided on the probe card, with a pull down termination circuit included in the test system controller. The test system controller can provide compensation for the base to emitter voltage drop of the emitter follower transistor.

摘要翻译： 在DUT和测试系统控制器之间的晶片测试系统的通道中提供射极跟随器或源极跟随器晶体管，以使低功率DUT能够驱动测试系统通道。 在射极跟随器晶体管的基极和发射极之间包括一个旁路电阻，以便能够在DUT通道和测试系统控制器之间提供双向信号，以及执行参数测试。 射极跟随器晶体管和旁路电阻可以在探针卡上提供，测试系统控制器中包含一个下拉终端电路。 测试系统控制器可以为射极跟随器晶体管的基极到发射极电压降提供补偿。