公开(公告)号：US20150285854A1

公开(公告)日：2015-10-08

申请号：US13635683

申请日：2011-03-16

Applicant: Mark A. Kassab ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Janusz Rajski ,  Jakub Janicki ,  Tyszer Jerzy

Inventor： Mark A. Kassab ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Janusz Rajski ,  Jakub Janicki ,  Tyszer Jerzy

IPC: G01R31/28

CPC classification number: G01R31/2834 ,  G01R31/2851 ,  G01R31/318335 ,  G01R31/318547 ,  G01R31/31921

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.

Abstract translation: 公开了测试压缩环境中用于测试调度和测试访问的方法，装置和系统的代表性实施例。 基于包括压缩测试数据，对应的测试仪通道要求和相关核心的测试信息形成用于测试电路中的多个核心的测试模式的集群。 测试模式集群的形成之后是测试者信道分配。 可以采用最佳拟合方案或平衡拟合方案来产生信道分配信息。 可以基于信道分配信息来设计用于动态信道分配的测试接入电路。

公开(公告)号：US09151804B2

公开(公告)日：2015-10-06

申请号：US13443919

申请日：2012-04-11

Applicant: Dietmar Orendi ,  Biren Minhas ,  Robert Baraniecki

Inventor： Dietmar Orendi ,  Biren Minhas ,  Robert Baraniecki

IPC: G01R19/00 ,  G01R31/40 ,  G01R31/317

CPC classification number: G01R31/40 ,  G01R31/2834 ,  G01R31/31721 ,  G05F1/56

Abstract: A circuit and method is described for automatically testing multiple LDO regulator circuits on an integrated circuit chip independent of an ATE. Each LDO regulator is tested for voltage at a specified current output capability, wherein the output driver transistor is formed by at least two pass transistors, which are each tested for voltage output at a particular current capability. The test results are delivered back to the ATE and for a failed test, the gate voltage of the pass device can be observed through an analog multiplexer to enable debug.

Abstract translation: 描述了一种用于在独立于ATE的集成电路芯片上自动测试多个LDO稳压器电路的电路和方法。 每个LDO调节器以指定的电流输出能力测试电压，其中输出驱动器晶体管由至少两个传输晶体管形成，每个晶体管都以特定电流能力测试电压输出。 测试结果被传送回ATE，对于失败的测试，可以通过模拟多路复用器观察通过器件的栅极电压，以启用调试。

公开(公告)号：US20150276809A1

公开(公告)日：2015-10-01

申请号：US14739314

申请日：2015-06-15

Applicant: Advantest Corporation

Inventor： Randy BARSATAN

IPC: G01R1/067 ,  G01R31/28

CPC classification number: G01R1/06772 ,  G01R1/06766 ,  G01R31/2834 ,  G01R31/31905 ,  G01R31/31908

Abstract: Embodiments of the present invention provide an RF probe for coupling out a probe signal from a transmission line of a circuit. The RF probe includes at least two probe pins having first ends for contacting the circuit and second ends. Furthermore, the RF probe includes a provider for providing a variable impedance at the second ends of the probe pins. The RF probe is configured to provide the probe signal based on a signal propagating along at least one of the probe pins.

Abstract translation: 本发明的实施例提供了一种用于耦合出来自电路的传输线的探测信号的RF探针。 RF探针包括至少两个探针，其具有用于接触电路和第二端的第一端。 此外，RF探头包括用于在探针的第二端处提供可变阻抗的提供器。 RF探针被配置为基于沿着至少一个探针的传播的信号来提供探测信号。

公开(公告)号：US20150177315A1

公开(公告)日：2015-06-25

申请号：US14138567

申请日：2013-12-23

Applicant: Keysight Technologies, Inc.

Inventor： Su Ann Lim ,  Ghazali Bin Hussin ,  Hwei Liat Law ,  Wei Zhi Ng

IPC: G01R31/28

CPC classification number: G01R31/2834 ,  G01R21/10

Abstract: A method is provided for dynamically determining measurement uncertainty (MU) of a measurement device for measuring a signal output by a device under test (DUT). The method includes storing characterized test data in a nonvolatile memory in the measurement device, the characterized test data being specific to the measurement device for a plurality of sources of uncertainty; receiving a parameter value of the DUT; measuring the signal output by the DUT and received by the measurement device; and calculating the measurement uncertainty of the measurement device for measuring the received signal using the stored characterized test data and the received parameter value of the DUT.

Abstract translation: 提供了一种用于动态地确定用于测量由被测器件（DUT）输出的信号的测量装置的测量不确定度（MU）的方法。 该方法包括将特征测试数据存储在测量装置中的非易失性存储器中，所述特征测试数据特定于测量装置用于多个不确定性源; 接收DUT的参数值; 测量由DUT测量并由测量装置接收的信号; 以及使用所存储的特征测试数据和所接收的DUT的参数值来计算用于测量接收信号的测量装置的测量不确定度。

公开(公告)号：US20150134287A1

公开(公告)日：2015-05-14

申请号：US14075271

申请日：2013-11-08

Applicant: Advantest (Singapore) Pte. Ltd.

Inventor： Thien NGO

IPC: G01R35/00 ,  G01R31/26 ,  G01R31/28

CPC classification number: G01R35/007 ,  G01R19/10 ,  G01R31/2601 ,  G01R31/2834 ,  G01R31/2851

Abstract: A method of error correction in automated test equipment (ATE) is presented. The method comprises calibrating the ATE using a calibration board, wherein the calibration board comprises a reference voltage. The calibrating comprises: (a) measuring the reference voltage using a reference channel and each of a plurality of channels in the ATE; (b) recording a series of differential voltage measurement values obtained from the measuring in a calibration module; and (c) calculating a respective correction factor for each of the plurality of channels utilizing the series of differential voltage measurement values. The method further comprises obtaining a measured voltage value for a DUT connected to a first channel in the ATE, wherein the first channel is one of the plurality of channels. Finally, the method comprises correcting the measured voltage value using a respective correction factor for said first channel.

Abstract translation: 介绍了自动化测试设备（ATE）中的纠错方法。 该方法包括使用校准板校准ATE，其中校准板包括参考电压。 校准包括：（a）使用参考通道和ATE中的多个通道中的每一个来测量参考电压; （b）在校准模块中记录从所述测量获得的一系列差分电压测量值; 和（c）利用一系列差分电压测量值来计算多个通道中的每个通道的各自的校正因子。 该方法还包括获得连接到ATE中的第一信道的DUT的测量电压值，其中第一信道是多个信道之一。 最后，该方法包括使用针对所述第一通道的相应校正因子校正所测量的电压值。

公开(公告)号：US09002673B2

公开(公告)日：2015-04-07

申请号：US13025657

申请日：2011-02-11

Applicant: Arya Reza Behzad ,  Ahmadreza Rofougaran ,  Sam Ziqun Zhao ,  Jesus Alfonso Castaneda ,  Michael Boers

Inventor： Arya Reza Behzad ,  Ahmadreza Rofougaran ,  Sam Ziqun Zhao ,  Jesus Alfonso Castaneda ,  Michael Boers

IPC: G01R31/14 ,  G01R31/28 ,  G01R31/302 ,  G01R31/311

CPC classification number: G01R31/2834 ,  G01R31/3025 ,  G01R31/311

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Abstract translation: 公开了同时无线地测试形成在半导体晶片上的半导体元件的方法和装置。 半导体部件通过公共通信信道将各自的测试结果传送到无线自动测试设备。 多个接收天线在三维空间中观察多个方向的结果。 无线自动测试设备确定一个或多个半导体组件是否按预期运行，并且可选地，可以使用三维空间的属性来确定一个或多个半导体组件的位置。 无线测试设备还可以通过检测在独立测试操作之前，期间和/或之后由半导体晶片发射，传输和/或反射的红外能量来确定半导体组件的性能。

公开(公告)号：US20150088437A1

公开(公告)日：2015-03-26

申请号：US14036709

申请日：2013-09-25

Applicant: Cavium, Inc.

Inventor： David Lin

IPC: G01R31/28 ,  G11C29/56 ,  H01L21/66

CPC classification number: G01R31/2834 ,  G11C29/022 ,  G11C29/023 ,  G11C29/56012 ,  G11C2029/5602

Abstract: In an embodiment, a memory interface includes integrated circuitry to verify the integrity of the memory interface. The circuitry propagates a test pattern through different paths of the memory interface, and checks the result against a reference value to determine whether the components of the paths are operating within an acceptable tolerance. The memory interface can also communicate with ATE to initiate such tests and return the results to the ATE.

Abstract translation: 在一个实施例中，存储器接口包括用于验证存储器接口的完整性的集成电路。 电路通过存储器接口的不同路径传播测试模式，并根据参考值检查结果，以确定路径的组件是否在可接受的公差范围内运行。 存储器接口还可以与ATE进行通信，以启动此类测试并将结果返回给ATE。

公开(公告)号：US08981807B2

公开(公告)日：2015-03-17

申请号：US13190928

申请日：2011-07-26

Applicant: Christopher Leonard West ,  Charles Paul Nappen

Inventor： Christopher Leonard West ,  Charles Paul Nappen

IPC: G01R31/20 ,  G01R31/28

CPC classification number: G01R31/2887 ,  B25J9/023 ,  B25J9/041 ,  B25J17/0208 ,  B25J19/002 ,  G01R31/2834 ,  G01R31/2891

Abstract: A system for positioning a load including a support column, a drive rail unit coupled to the support column, the drive rail unit moveable relative to the support column, a vertical carriage moveable along the support column, wherein the vertical carriage supports the load, an engagement member which engages the drive rail and which moves along the drive rail, and a motor which applies force to the engagement member, causing the engagement member to move along the drive rail. The motor is coupled to the vertical carriage so that, as the motor applies force to the engagement member, the vertical carriage moves relative to the drive rail unit, the vertical carriage is also moveable with the drive rail unit so that the vertical carriage and the drive rail unit move relative to the support column. A method of positioning a load is also provided.

Abstract translation: 一种用于定位负载的系统，包括支撑柱，耦合到支撑柱的驱动轨单元，可相对于支撑柱移动的驱动轨道单元，可沿着支撑柱移动的竖直托架，其中竖直托架支撑负载， 接合构件，其与驱动轨道接合并沿着驱动轨道移动;以及电动机，其向接合构件施加力，使得接合构件沿着驱动轨道移动。 电动机联接到垂直滑架，使得当电动机对接合构件施加力时，垂直滑架相对于驱动轨道单元移动，垂直滑架也可以与驱动轨道单元一起移动，使得垂直滑架和 驱动轨道单元相对于支撑柱移动。 还提供了一种定位负载的方法。

公开(公告)号：US08942946B2

公开(公告)日：2015-01-27

申请号：US12945736

申请日：2010-11-12

Applicant: Kazumoto Tamura

Inventor： Kazumoto Tamura

IPC: G06F19/00 ,  G01R31/319 ,  G01R31/28 ,  G06F11/273 ,  H04L12/26 ,  G06F11/277

CPC classification number: G01R31/31907 ,  G01R31/2834 ,  G01R31/2851 ,  G01R31/319 ,  G01R31/31919 ,  G01R31/31926 ,  G06F11/273 ,  G06F11/2733 ,  G06F11/277 ,  H04L43/50

Abstract: Provided is a test apparatus that tests a device under test, comprising a test unit that sends and receives signals to and from the device under test; a control apparatus that controls the test unit; and a relay apparatus that relays between the control apparatus and the test unit. The relay apparatus includes a first communicating section that receives a command from the control apparatus to the relay apparatus and transmits the command to the test unit; a second communicating section that receives a return command that is transmitted back to the relay apparatus by the test unit that received the command; and an executing section that executes a process designated by the return command, in response to the second communicating section receiving the return command.

Abstract translation: 提供了一种测试被测设备的测试设备，包括：向被测设备发送和接收信号的测试单元; 控制所述测试单元的控制装置; 以及在控制装置和测试单元之间中继的中继装置。 所述中继装置包括：第一通信部，其从所述控制装置接收到所述中继装置的指令，并将所述命令发送到所述测试部; 第二通信部，其接收由接收到所述命令的所述测试单元发送回所述中继装置的返回命令; 以及执行部，响应于所述第二通信部接收到所述返回命令，执行由所述返回命令指定的处理。

公开(公告)号：US20150025829A1

公开(公告)日：2015-01-22

申请号：US14507856

申请日：2014-10-07

Applicant: MediaTek Singapore Pte. Ltd.

Inventor： Uming Ko ,  Gordon Gammie ,  Alice Wang

IPC: G01R31/317 ,  G01R31/28

CPC classification number: G05F1/462 ,  G01R31/2834 ,  G01R31/31721 ,  G01R31/31724 ,  G05F1/46 ,  G06F1/206 ,  G06F1/26 ,  Y02D10/16

Abstract: The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC maybe set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC.

Abstract translation: 性能，热和电源管理系统配置为在IC中进行DVFS校准，温度补偿调整，老化校准和直流偏移校准。 提供给IC的初始电压可以设置为考虑到芯片到芯片工艺变化的初始值，然后根据温度变化，DC偏移和/或老化效应动态地调整。 因此，性能，热和电源管理系统可以实现IC的优化的热和功率性能。