公开(公告)号：US09331665B2

公开(公告)日：2016-05-03

申请号：US13887568

申请日：2013-05-06

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik D. Kim ,  Je-Hsiung Lan ,  Jonghae Kim ,  Mario Francisco Velez ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

公开(公告)号：US09324779B2

公开(公告)日：2016-04-26

申请号：US14063934

申请日：2013-10-25

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Daeik Daniel Kim ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Mario Francisco Velez ,  Chengjie Zuo ,  Changhan Hobie Yun

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/64

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor.

Abstract translation: 一些新颖的特征涉及包括衬底，通过衬底的第一腔和围绕衬底的第一腔配置的环形电感器的集成器件。 环形电感器包括围绕第一腔配置的一组绕组。 该组绕组包括在衬底的第一表面上的第一组互连，一组通过衬底通孔（TSV）和在衬底的第二表面上的第二组互连。 第一组互连通过集合TSV耦合到第二组互连。 在一些实施方案中，集成器件还包括位于第一腔内的互连材料（例如，焊球）。 互连材料被配置为将管芯耦合到印刷电路板。 在一些实施方案中，互连材料是环形电感器的一部分。

公开(公告)号：US20150061813A1

公开(公告)日：2015-03-05

申请号：US14155244

申请日：2014-01-14

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Xiangdong Zhang ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H01F27/28 ,  H01F41/04

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F27/2804 ,  H01F41/042 ,  H01F2017/0053 ,  H01F2017/0073 ,  H01F2027/2809

Abstract: A particular device includes a substrate and a spiral inductor coupled to the substrate. The spiral inductor includes a first conductive spiral and a second conductive spiral overlaying the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate that is greater than the first thickness. A portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.

Abstract translation: 特定器件包括衬底和耦合到衬底的螺旋电感器。 螺旋电感器包括覆盖第一导电螺旋的第一导电螺旋和第二导电螺旋。 螺旋电感器的最内圈的第一部分在垂直于衬底的方向上具有第一厚度。 最内圈的第一部分包括第一导电螺旋的第一部分，并且不包括第二导电螺旋。 最内圈的第二部分包括第二导电螺旋的第一部分。 螺旋电感器的最外圈的一部分在垂直于衬底的方向上具有大于第一厚度的第二厚度。 最外圈的一部分包括第一导电螺旋的第二部分和第二导电螺旋的第二部分。

公开(公告)号：US20140327496A1

公开(公告)日：2014-11-06

申请号：US13887568

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Chengjie Zuo ,  Daeik D. Kim ,  Je-Hsiung Lan ,  Jonghae Kim ,  Mario Francisco Velez ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46 ,  H03H3/00

CPC classification number: H03H7/461 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  Y10T29/49016

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

Abstract translation: 公开了三维（3D）集成电路（IC）（3DIC）中的可调谐双工器。 在一个实施例中，可调谐双工器可以通过在双工器中提供变容二极管或可变电感器之一来形成。 可变电抗器或可变电感器的可变特性允许调谐双工器中的陷波，以便选择频带停止以消除期望频率处的谐波以及控制通带的截止频率。 通过将双工器的元件堆叠成三维空间是保守的，并且可以使用各种变容二极管和电感器。

公开(公告)号：US20140266494A1

公开(公告)日：2014-09-18

申请号：US13829784

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Je-Hsiung Lan ,  Chi Shun Lo ,  Jonghae Kim ,  Mario Francisco Velez ,  John H. Hong

IPC: H03H11/28 ,  H01L21/84

CPC classification number: H03H11/28 ,  H01F41/02 ,  H01F2019/085 ,  H01F2027/2809 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L27/13 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/30111 ,  H01L2924/00

Abstract: A particular device includes a replica circuit disposed above a dielectric substrate. The replica circuit includes a thin film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The device further includes a transformer disposed above the dielectric substrate and coupled to the replica circuit. The transformer is configured facilitate an impedance match between the replica circuit and an antenna.

Abstract translation: 特定装置包括设置在电介质基板上方的复制电路。 复制电路包括被配置为用作可变电容器或可变电阻器的薄膜晶体管（TFT）。 该装置还包括设置在电介质基板上方并耦合到复制电路的变压器。 变压器配置有助于复制电路和天线之间的阻抗匹配。

公开(公告)号：US12273095B2

公开(公告)日：2025-04-08

申请号：US17245901

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Kai Liu ,  Rui Tang ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H03H3/02 ,  H01P1/203 ,  H03H9/05 ,  H03H9/54

Abstract: Aspects of the disclosure are directed to a bandpass filter including a first, second, third and fourth resonators, wherein the second and third resonators are in parallel, wherein the first resonator includes a first and second terminals, wherein the second resonator includes a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator includes a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator includes a third terminal and a fourth terminal; wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to the third resonator top terminal, wherein the third terminal is coupled to the third resonator bottom terminal, wherein the fourth terminal is coupled to the second resonator bottom terminal; a first inductor coupled to the first and third terminals; and a second inductor coupled to the second and fourth terminals.

公开(公告)号：US11121699B2

公开(公告)日：2021-09-14

申请号：US16279902

申请日：2019-02-19

Applicant: QUALCOMM Incorporated

Inventor： Kai Liu ,  Rui Tang ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H03H9/54 ,  H03H9/05 ,  H03H3/02 ,  H01P1/203

Abstract: Aspects of the disclosure are directed to a bandpass filter including a first, second, third and fourth resonators, wherein the second and third resonators are in parallel, wherein the first resonator includes a first and second terminals, wherein the second resonator includes a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator includes a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator includes a third terminal and a fourth terminal; wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to the third resonator top terminal, wherein the third terminal is coupled to the third resonator bottom terminal, wherein the fourth terminal is coupled to the second resonator bottom terminal; a first inductor coupled to the first and third terminals; and a second inductor coupled to the second and fourth terminals.

公开(公告)号：US10734332B2

公开(公告)日：2020-08-04

申请号：US15839831

申请日：2017-12-12

Applicant: QUALCOMM Incorporated

Inventor： Jon Bradley Lasiter ,  Ravindra Vaman Shenoy ,  Donald William Kidwell, Jr. ,  Mohammad Ali Tassoudji ,  Vladimir Aparin ,  Seong Heon Jeong ,  Jeremy Dunworth ,  Alireza Mohammadian ,  Mario Francisco Velez ,  Chin-Kwan Kim

IPC: H01L23/00 ,  H01L23/66 ,  H01L23/498 ,  H01L23/552 ,  H01L23/31 ,  H01L21/50 ,  H01Q1/22 ,  H01Q1/24 ,  H01Q21/10 ,  H01Q19/24 ,  H01Q9/16 ,  H01L23/10

Abstract: In conventional packaging strategies for mm wave applications, the size of the package is dictated by the antenna size, which is often much larger than the RFIC (radio frequency integrated circuit). Also, the operations are often limited to a single frequency which limits their utility. In addition, multiple addition build-up layers are required to provide the necessary separation between the antennas and ground layers. To address these issues, it is proposed to provide a device that includes an antenna package, an RFIC package, and an interconnect assembly between the antenna and the RFIC packages. The interconnect assembly may comprise a plurality of interconnects with high aspect ratios and configured to connect one or more antennas of the antenna package with an RFIC of the RFIC package. An air gap may be formed in between the antenna package and the RFIC package for performance improvement.

公开(公告)号：US10553671B2

公开(公告)日：2020-02-04

申请号：US15178900

申请日：2016-06-10

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez

IPC: H01L29/00 ,  H01L49/02 ,  H01L21/48 ,  H01F17/00 ,  H01L23/522 ,  H01L23/498 ,  H01L23/48 ,  H01L23/64 ,  H01F27/28 ,  H01L23/00

Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

公开(公告)号：US10319694B2

公开(公告)日：2019-06-11

申请号：US15233902

申请日：2016-08-10

Applicant: QUALCOMM Incorporated

Inventor： Daniel Daeik Kim ,  Jie Fu ,  Manuel Aldrete ,  Jonghae Kim ,  Changhan Hobie Yun ,  David Francis Berdy ,  Chengjie Zuo ,  Mario Francisco Velez

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package substrate with a first set of contacts on an active side of the semiconductor die and coupled to a plurality of solder prints with a second set of contacts on a back side of the semiconductor die. The semiconductor die may include a plurality of vias connecting the first set of contacts to the second set of contacts and configured to allow heat to be transferred from the active side of the die to the plurality of solder prints for a shorter heat dissipation path.