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公开(公告)号：US20240397226A1
公开(公告)日：2024-11-28
申请号：US18322431
申请日：2023-05-23
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Jiayu Guo , Hiroaki Ebihara , Liang Zuo , Lihang Fan , Satoshi Sakurai
Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.
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公开(公告)号：US20240284074A1
公开(公告)日：2024-08-22
申请号：US18171227
申请日：2023-02-17
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang , Hiroaki Ebihara
Abstract: A pixel cell readout circuit comprises a comparator with a current mirror having first and second current paths, a first input transistor coupled to the first current path, a low conversion gain (LCG) second input transistor selectively coupled to the second current path, and a high conversion gain (HCG) second input transistor selectively coupled to the second current path. The pixel cell readout circuit further comprises a gain network coupled between a gate node of the first input transistor and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator, an LCG auto-zero switch coupled between a drain node and a gate node of the LCG second input transistor, and an HCG auto-zero switch coupled between a drain node and a gate node of the HCG second input transistor.
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公开(公告)号：US20230336889A1
公开(公告)日：2023-10-19
申请号：US17719602
申请日：2022-04-13
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Zhenfu Tian , Hiroaki Ebihara , Tao Sun , Yi Liu , Shan Chen
CPC classification number: H04N5/378 , H03K4/08 , H04N5/3765
Abstract: A ramp generator includes an operational amplifier having an output to generate a ramp signal. An integration current source is coupled to a first input and a reference voltage is coupled to a second input of the operational amplifier. A feedback capacitor is coupled between the first input and the output of the operational amplifier. A monitor circuit is coupled to the first and second inputs of the operational amplifier to generate an output flag in response to a comparison of the first and second inputs. A trimming control circuit is configured to generate a trimming signal in response to the output flag. An assist current source is configured to conduct an assist current from the output of the operational amplifier to ground in response the trimming signal generated by the trimming control circuit.
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64.发明公开公开(公告)号：US20230328405A1
公开(公告)日：2023-10-12
申请号：US17658559
申请日：2022-04-08
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Xuelian Liu , Min Qu , Liang Zuo , Selcuk Sen , Hiroaki Ebihara , Rui Wang , Lihang Fan
CPC classification number: H04N5/3698 , H04N5/36961 , H04N5/378
Abstract: An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.
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公开(公告)号：US11729529B1
公开(公告)日：2023-08-15
申请号：US17825797
申请日：2022-05-26
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Zhe Gao , Hiroaki Ebihara , Ling Fu , Tiejun Dai
IPC: H04N25/75 , H04N25/53 , H04N25/62 , H04N25/65 , H04N25/771 , H04N25/532
CPC classification number: H04N25/75 , H04N25/53 , H04N25/62 , H04N25/65 , H04N25/771
Abstract: A global shutter readout circuit includes a reset transistor coupled between a reset voltage and a bitline. A pixel enable transistor is coupled between the reset transistor and a source follower transistor. First and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor. A first storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A first storage capacitor is coupled to the first storage transistor. A second storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A second storage capacitor is coupled to the second storage transistor. A row select transistor is coupled to the source follower transistor to generate an output signal from the global shutter readout circuit.
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Patent Agency Ranking
公开(公告)号：US11683604B1
公开(公告)日：2023-06-20
申请号：US17678533
申请日：2022-02-23
Applicant: OmniVision Technologies, Inc.
Inventor： Liang Zuo , Rui Wang , Selcuk Sen , Xuelian Liu , Min Qu , Hiroaki Ebihara
IPC: H04N25/704 , H04N25/11 , H04N25/60
CPC classification number: H04N25/704 , H04N25/11 , H04N25/60
Abstract: An image sensor includes an array of multiple-photodiode cells, each photodiode coupled through a selection transistor to a floating diffusion of the cell, the selection transistors controlled by respective transfer lines, a reset, a sense source follower, and a read transistor coupled from the source follower to a data line. The array includes phase detection rows with phase detection cells and normal cells; and a compensation row of more cells. In embodiments, each phase detection row has cells with at least one photodiode coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the row. In embodiments, the compensation row has cells with photodiodes coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the compensation row.
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公开(公告)号：US11240458B2
公开(公告)日：2022-02-01
申请号：US16900576
申请日：2020-06-12
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Hiroaki Ebihara , Rui Wang , John Brummer , Shan Chen
Abstract: A pixel cell readout circuit includes a bitline input stage coupled to a bitline to receive an image signal from a pixel cell. A capacitor ratio circuit is coupled to the bitline input stage. A gain of the bitline input stage is responsive to a capacitor ratio provided by the capacitor ratio circuit to the bitline input stage. A switch control circuit is coupled to receive a gain signal. The switch control circuit is coupled to generate a randomized pattern selection signal coupled to be received by the capacitor ratio circuit to select the capacitor ratio provided by the capacitor ratio circuit in response to the gain signal.
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公开(公告)号：US20210360175A1
公开(公告)日：2021-11-18
申请号：US17066200
申请日：2020-10-08
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Tiejun Dai , Hiroaki Ebihara , Sang Joo Lee , Rui Wang , Hiroki Ui
Abstract: A pixel array includes pixel cells, each including photodiodes. A source follower is coupled to generate an image signal in response image charge generated by the photodiodes. A first row select transistor is coupled to the source follower to output the image signal of the pixel cell. Pixel cells are organized into columns including a first column and a second column. The first row select transistors of the pixel cells of the first and second columns of pixel cells are coupled to first and second column bitlines, respectively. The pixel cells of the second column of pixel cells further include a second row select transistor coupled to the source follower to output the respective image signal to the first column bitline.
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公开(公告)号：US11095836B2
公开(公告)日：2021-08-17
申请号：US16685663
申请日：2019-11-15
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang , Hiroaki Ebihara , Zhiyong Zhan , Liang Zuo , Min Qu , Wanqing Xin , Xuelian Liu
Abstract: An image sensor includes a pixel array with rows and columns of pixels. Each row of the pixel array has a first end that is opposite a second end of each row of the pixel array. Control circuitry is coupled to the first end of each row of the pixel array to provide control signals to each row of the pixel array from the first end of each row of the pixel array. Far end driver circuitry coupled to the second end of each row of the pixel array to selectively further drive from the second end of each row of the pixel array the control signals provided by the control circuitry from the first end of each row of the pixel array. The control circuitry is further coupled to provide far end control signals to the far end driver circuitry.
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公开(公告)号：US10951840B1
公开(公告)日：2021-03-16
申请号：US16555796
申请日：2019-08-29
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang , Hiroaki Ebihara , Eiichi Funatsu
IPC: H04N5/347 , H04N5/378 , H01L27/146
Abstract: A photodiode array circuit includes a plurality of photodiode circuits, binning circuitry, and a plurality of output circuits. Each of the plurality of photodiode circuits is coupled to receive a different one of the plurality of transfer control signals as a proximate photodiode circuit, proximate in a first direction. The binning circuitry is coupled to electrically connect the plurality of photodiode circuits into groups of photodiode circuit sense nodes in response to a binning control signal. Each of the plurality of output circuits is coupled to one of the groups of photodiode circuit sense nodes. Each of the plurality of output circuits are coupled to receive the output charge from the photodiode circuits in the one of the groups of photodiode circuit sense nodes and output an output signal to a bitline in response to the output charge and an row select signal.
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