公开(公告)号：US06914012B2

公开(公告)日：2005-07-05

申请号：US10879440

申请日：2004-06-29

Applicant: Matthias Passlack ,  Nicholas William Medendorp, Jr.

Inventor： Matthias Passlack ,  Nicholas William Medendorp, Jr.

IPC: C23C14/08 ,  C30B23/02 ,  C30B29/16 ,  H01L21/28 ,  H01L21/31 ,  H01L21/316 ,  H01L29/423 ,  H01L29/51 ,  H01L21/469

CPC classification number: H01L29/513 ,  C23C14/08 ,  C30B23/02 ,  C30B29/16 ,  H01L21/02112 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02269 ,  H01L21/28194 ,  H01L21/28264 ,  H01L21/31604 ,  H01L21/31666 ,  H01L29/4232 ,  H01L29/511 ,  H01L29/517

Abstract: A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor structure to form an interface therewith. A second layer of a Ga—Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor, a heterojunction bipolar transistor, or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga—Gd-oxide. The Ga2O3 layer is used to form a high quality interface with the GaAs-based supporting semiconductor structure while the Ga—Gd-oxide provides a low oxide leakage current density.

Abstract translation: 提供了一种化合物半导体结构，其包括具有其上将要形成介电材料的表面的GaAs基支撑半导体结构。 第一层氧化镓位于支撑半导体结构的表面上以与其形成界面。 在第一层上设置第二层Ga-Gd氧化物。 GaAs基支撑半导体结构可以是诸如至少部分完成的半导体器件（例如，金属氧化物场效应晶体管，异质结双极晶体管或半导体激光器）的基于GaAs的异质结构。 以这种方式，提供了在氧化物 - GaAs界面处具有低缺陷密度和低氧化物漏电流密度的电介质层结构，因为电介质结构由Ga 2 O 2层形成， 然后是一层Ga-Gd氧化物。 Ga 2 O 3层用于与GaAs基支持半导体结构形成高质量的界面，而Ga-Gd氧化物提供低的氧化物漏电流密度 。

公开(公告)号：US6094295A

公开(公告)日：2000-07-25

申请号：US022703

申请日：1998-02-12

Applicant: Matthias Passlack ,  Jonathan Kwadwo Abrokwah ,  Zhiyi Jimmy Yu

Inventor： Matthias Passlack ,  Jonathan Kwadwo Abrokwah ,  Zhiyi Jimmy Yu

IPC: C23C14/08 ,  H01L21/316 ,  H01L31/0224 ,  H01L31/18 ,  G02F1/00 ,  B05D3/06 ,  H01L21/31 ,  H01L29/94

CPC classification number: C23C14/08 ,  H01L21/31604 ,  H01L31/022466 ,  H01L31/1884 ,  Y02E10/50

Abstract: An electro-conductive ultraviolet light transmitting Ga.sub.2 O.sub.3 material (10) with a metallic oxide phase is deposited on a GaAs substrate or supporting structure (12). The Ga.sub.2 O.sub.3 material or thin layer comprises a minor component of metallic IrO.sub.2. The Ga.sub.2 O.sub.3 thin layer may be positioned using thermal evaporation (106) of Ga.sub.2 O.sub.3 or of a Ga.sub.2 O.sub.3 containing a compound from an Iridium crucible (108). Alternatively, the Ir may be co-evaporated (110) by electron beam evaporation. The electro-conductive ultraviolet light transmitting material Ga.sub.2 O.sub.3 with a metallic oxide phase is suitable for use on solar cells and in laser lithography.

Abstract translation: 在GaAs衬底或支撑结构（12）上沉积具有金属氧化物相的透射Ga 2 O 3材料（10）的导电紫外光。 Ga 2 O 3材料或薄层包含金属IrO 2的次要组分。 可以使用Ga 2 O 3的热蒸发（106）或含有来自铱坩埚（108）的化合物的Ga 2 O 3来定位Ga 2 O 3薄层。 或者，Ir可以通过电子束蒸发共蒸发（110）。 具有金属氧化物相的导电紫外线透射材料Ga 2 O 3适用于太阳能电池和激光光刻。

公开(公告)号：US5945718A

公开(公告)日：1999-08-31

申请号：US22593

申请日：1998-02-12

Applicant: Matthias Passlack ,  Jonathan Kwadwo Abrokwah ,  Zhiyi Yu

Inventor： Matthias Passlack ,  Jonathan Kwadwo Abrokwah ,  Zhiyi Yu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H07L29/78

CPC classification number: H01L29/517 ,  H01L21/28158 ,  H01L29/66522

Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor FET (10) includes a stoichiometric Ga.sub.2 O.sub.3 gate oxide layer (14) positioned on upper surface (16) of a compound semiconductor wafer structure (13). The stoichiometric Ga.sub.2 O.sub.3 layer forms an atomically abrupt interface with the compound semiconductor wafer structure. A refractory metal gate electrode (17) is positioned on upper surface (18) of the stoichiometric Ga.sub.2 O.sub.3 gate oxide layer (14). The refractory metal is stable on the stoichiometric Ga.sub.2 O.sub.3 gate oxide layer at elevated temperature. Self-aligned source and drain areas, and source and drain contacts (19, 20) are positioned on the source and drain areas (21, 22).

Abstract translation: 自对准增强型金属氧化物半导体FET（10）包括位于化合物半导体晶片结构（13）的上表面（16）上的化学计量的Ga 2 O 3栅极氧化物层（14）。 化学计量的Ga 2 O 3层与化合物半导体晶片结构形成原子突变的界面。 难熔金属栅电极（17）位于化学计量的Ga 2 O 3栅极氧化物层（14）的上表面（18）上。 难熔金属在高温下在化学计量的Ga 2 O 3栅极氧化物层上是稳定的。 自对准源极和漏极区以及源极和漏极接触（19,20）位于源极和漏极区域（21,22）上。

公开(公告)号：US5907792A

公开(公告)日：1999-05-25

申请号：US917122

申请日：1997-08-25

Applicant: Ravi Droopad ,  Jonathan K. Abrokwah ,  Matthias Passlack ,  Zhiyi Jimmy Yu

Inventor： Ravi Droopad ,  Jonathan K. Abrokwah ,  Matthias Passlack ,  Zhiyi Jimmy Yu

IPC: C23C14/06 ,  H01L21/318 ,  H01L29/78

CPC classification number: C23C14/0652 ,  H01L21/3185 ,  Y10S148/169 ,  Y10S438/961

Abstract: A method of forming a silicon nitride layer or film on a semiconductor wafer structure includes forming a silicon nitride layer on the surface of a wafer structure using a molecular beam of high purity elemental Si and an atomic beam of high purity nitrogen. In a preferred embodiment, a III-V compound semiconductor wafer structure is heated in an ultra high vacuum system to a temperature below the decomposition temperature of said compound semiconductor wafer structure and a silicon nitride layer is formed using a molecular beam of Si provided by either thermal evaporation or electron beam evaporation, and an atomic nitrogen beam provided by either RF or microwave plasma discharge.

Abstract translation: 在半导体晶片结构上形成氮化硅层或膜的方法包括使用高纯度元素Si的分子束和高纯氮原子束在晶片结构的表面上形成氮化硅层。 在优选实施例中，III-V族化合物半导体晶片结构在超高真空系统中被加热至低于所述化合物半导体晶片结构的分解温度的温度，并且使用由以下两者之一提供的Si的分子束形成氮化硅层 热蒸发或电子束蒸发，以及由RF或微波等离子体放电提供的原子氮光束。

公开(公告)号：US5902130A

公开(公告)日：1999-05-11

申请号：US896234

申请日：1997-07-17

Applicant: Matthias Passlack ,  Jonathan K. Abrokwah ,  Zhiyi Jimmy Yu

Inventor： Matthias Passlack ,  Jonathan K. Abrokwah ,  Zhiyi Jimmy Yu

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/26553 ,  H01L29/66522 ,  H01L29/517 ,  H01L29/518

Abstract: A method of thermal processing a supporting structure comprised of various compound semiconductor layers having a Gd free Ga.sub.2 O.sub.3 surface layer including coating the surface layer with a dielectric or a metallic cap layer or combinations thereof, such that the low D.sub.it Ga.sub.2 O.sub.3 -compound semiconductor structure is conserved during thermal processing, e.g. during activation of ion implants of a self aligned metal-oxide-compound semiconductor gate structure. In a preferred embodiment, the semiconductor structure has a surface of GaAs, the Gd free Ga.sub.2 O.sub.3 layer has a thickness in a range of approximately 1 nm to 20 nm, and the insulating or metallic cap layer has a thickness in a range of approximately 1 nm to 500 nm.

Abstract translation: 一种热处理由具有Gd游离Ga 2 O 3表面层的各种化合物半导体层构成的支撑结构的方法，包括用电介质或金属覆盖层或其组合涂覆表面层，使得低Dit Ga 2 O 3化合物半导体结构被保守 在热处理过程中，例如 在自对准的金属氧化物 - 化合物半导体栅极结构的离子注入的激活期间。 在优选实施例中，半导体结构具有GaAs的表面，Gd自由的Ga 2 O 3层的厚度在约1nm至20nm的范围内，并且绝缘或金属覆盖层的厚度在约1nm的范围内 至500nm。

公开(公告)号：US5597768A

公开(公告)日：1997-01-28

申请号：US619400

申请日：1996-03-21

Applicant: Matthias Passlack ,  Jonathan K. Abrokwah

Inventor： Matthias Passlack ,  Jonathan K. Abrokwah

IPC: H01L21/316

CPC classification number: H01L21/31604 ,  Y10S148/118

Abstract: A method of forming a dielectric layer on a supporting structure of III-V material having a clean and atomically ordered surface to be coated with a dielectric layer including the step of depositing a layer of Ga.sub.2 O.sub.3, having a sublimation temperature, on the surface of the supporting structure by evaporation using a high purity single crystal of material including Ga.sub.2 O.sub.3 and a second oxide with a melting point greater than 700.degree. C. above the sublimation temperature of the Ga.sub.2 O.sub.3. The evaporation can be performed by any one of thermal evaporation, electron beam evaporation, and laser ablation.

Abstract translation: 在III-V族材料的支撑结构上形成电介质层的方法，所述III-V族材料具有要涂覆介电层的清洁且原子序列的表面，包括将具有升华温度的Ga 2 O 3层沉积在 通过使用包含Ga 2 O 3的高纯度单晶和熔点高于700℃以上的Ga 2 O 3的升华温度的第二氧化物通过蒸发进行支撑结构。 蒸发可以通过热蒸发，电子束蒸发和激光烧蚀中的任何一种进行。