公开(公告)号：US20090258492A1

公开(公告)日：2009-10-15

申请号：US12489337

申请日：2009-06-22

Applicant: Sanket Sant ,  Gurtej Sandhu ,  Neal R. Rueger

Inventor： Sanket Sant ,  Gurtej Sandhu ,  Neal R. Rueger

IPC: H01L21/306

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/76802 ,  H01L27/1052

Abstract: Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.

Abstract translation: 使用多个间距倍数的间隔物来形成具有特别小的临界尺寸的特征的掩模图案。 去除围绕多个心轴形成的每对间隔件中的一个，并且由两个相互选择性可蚀刻的材料形成的交替层围绕剩余的间隔物沉积。 然后蚀刻由一种材料形成的层，留下由形成掩模图案的另一种材料形成的垂直延伸层。 或者，代替沉积交替的层，非晶碳沉积在剩余的间隔物周围，随后在无定形碳上形成成对隔离物的多个循环，去除一对隔离物之一并沉积无定形碳层。 可以重复循环以形成所需的图案。 由于图案中的某些特征的临界尺寸可以通过控制间隔物之间​​的间隔的宽度来设定，所以可以形成特别小的掩模特征。

公开(公告)号：US20090035905A1

公开(公告)日：2009-02-05

申请号：US11832972

申请日：2007-08-02

Applicant: Ramakanth Alapati ,  Gurtej Sandhu

Inventor： Ramakanth Alapati ,  Gurtej Sandhu

IPC: H01L21/336

CPC classification number: H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: Briefly, in accordance with one or more embodiments, a method of making an inverse-t shaped floating gate in a non-volatile memory cell or the like is disclosed.

Abstract translation: 简而言之，根据一个或多个实施例，公开了在非易失性存储单元等中制造逆T形浮置栅极的方法。

公开(公告)号：US07452759B2

公开(公告)日：2008-11-18

申请号：US11288816

申请日：2005-11-29

Applicant: Gurtej Sandhu

Inventor： Gurtej Sandhu

IPC: H01L21/84

CPC classification number: H01L51/0512 ,  B82Y10/00 ,  H01L51/0048 ,  Y10S977/842 ,  Y10S977/938

Abstract: A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. In one embodiment, a method for forming a carbon nanotube transistor starts with a substrate comprised of a bottom dielectric, a carbon nanotube layer, and a top dielectric. A pillar is formed on the top dielectric, and a sidewall gate is formed on a sidewall of the pillar. A source is formed proximate to an outer edge of the gate and in contact with the carbon nanotube layer. The pillar is then removed, the source area masked, and a drain is formed proximate to an inner edge of the gate and in contact with the carbon nanotube layer. The source and drain are self aligned to the gate as dictated by the placement of dielectric spacers on the inner and outer edges of the gate.

Abstract translation: 本文公开了一种用于碳纳米管场效应晶体管的结构和制造方法。 在一个实施例中，用于形成碳纳米管晶体管的方法从由底部电介质，碳纳米管层和顶部电介质构成的衬底开始。 在顶部电介质上形成有支柱，并且在该支柱的侧壁上形成侧壁浇口。 源极靠近栅极的外边缘形成并与碳纳米管层接触。 然后移除柱，源区域被掩蔽，并且漏极形成在栅极的内边缘附近并与碳纳米管层接触。 源极和漏极与栅极自对准，这是由栅极的内部和外部边缘上的介质间隔物的放置所决定的。

公开(公告)号：US07444934B2

公开(公告)日：2008-11-04

申请号：US11135453

申请日：2005-05-24

Applicant: Gurtej Sandhu ,  Cem Basceri

Inventor： Gurtej Sandhu ,  Cem Basceri

IPC: B41F33/00

CPC classification number: B41F33/00 ,  B33Y40/00 ,  H01L21/288 ,  H01L21/76838 ,  H01L23/5328 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: High resolution patterns provided on a surface of a semiconductor substrate and methods of direct printing of such high resolution patterns are disclosed. The high resolution patterns may have dimensions less than 0.1 micron and are formed by a direct writing method employing a supercritical fluid comprising nanometer-sized particles, which may be optionally electrically charged.

Abstract translation: 公开了在半导体衬底的表面上提供的高分辨率图案以及直接印刷这种高分辨率图案的方法。 高分辨率图案可以具有小于0.1微米的尺寸，并且通过使用包含纳米尺寸颗粒的超临界流体的直接书写方法形成，所述超临界流体可以任选带电。

公开(公告)号：US07429536B2

公开(公告)日：2008-09-30

申请号：US11134982

申请日：2005-05-23

Applicant: Mirzafer Abatchev ,  Gurtej Sandhu

Inventor： Mirzafer Abatchev ,  Gurtej Sandhu

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L27/105 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form sumperimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.

Abstract translation: 公开了形成集成电路中使用的小密集间隔开的孔或柱的阵列的方法。 可以使用各种图案转移和蚀刻步骤，结合减音技术来产生密集包装的特征。 传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。

公开(公告)号：US20080089647A1

公开(公告)日：2008-04-17

申请号：US11951796

申请日：2007-12-06

Applicant: Gurtej Sandhu ,  Guy Blalock ,  Howard Rhodes

Inventor： Gurtej Sandhu ,  Guy Blalock ,  Howard Rhodes

IPC: G02B6/26

CPC classification number: G02B6/132 ,  G02B6/12004 ,  G02B6/12007 ,  G02B6/136 ,  G02F1/011 ,  G02F1/0147 ,  G02F2203/15

Abstract: A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is formed on a surface of the lower cladding. Since upper surfaces of the resonator and waveguide are substantially coplanar, the aspect ratio, as between the waveguide and resonator in an area where the waveguide and resonator front one another, decreases thereby increasing the bandwidth of the resonator. The depression is formed by photomasking and etching the lower cladding before forming the resonator and waveguide. Pluralities of resonators are also taught that are formed in a plurality of depressions of the lower cladding. To decrease resonator bandwidth, waveguide(s) are formed in the depression(s) of the lower cladding while the resonator is formed on the surface. Thermo optic devices formed with these resonators are also taught.

Abstract translation: 用于热光器件的谐振器以与波导相同的工艺步骤形成，并且形成在下包层的凹陷中，同时波导形成在下包层的表面上。 由于谐振器和波导的上表面基本上是共面的，因此在波导和谐振器彼此前向的区域中的波导和谐振器之间的纵横比减小，从而增加了谐振器的带宽。 在形成谐振器和波导之前，通过光掩模和蚀刻下部包层形成凹陷。 还教导了形成在下部包层的多个凹部中的多个谐振器。 为了减小谐振器带宽，当在表面上形成谐振器时，在下包层的凹陷中形成波导。 还教导了用这些谐振器形成的热光器件。

公开(公告)号：US20070284638A1

公开(公告)日：2007-12-13

申请号：US11728912

申请日：2007-03-27

Applicant: Gurtej Sandhu ,  Alan Reinberg

Inventor： Gurtej Sandhu ,  Alan Reinberg

IPC: H01L27/108

CPC classification number: H01L28/90 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91 ,  Y10S257/906

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

公开(公告)号：US20070275526A1

公开(公告)日：2007-11-29

申请号：US11837149

申请日：2007-08-10

Applicant: Cem Basceri ,  Gurtej Sandhu

Inventor： Cem Basceri ,  Gurtej Sandhu

IPC: H01L21/336

CPC classification number: G11C11/5671 ,  G11C8/12 ,  G11C16/0416 ,  G11C16/0466 ,  H01L29/513 ,  H01L29/792

Abstract: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.

Abstract translation: 单晶体管存储器件通过操纵场效应晶体管（FET）的俘获层内的氧空位来促进非易失性数据存储，从而提供晶体管的阈值电压的控制和变化。 可以为各种阈值电压分配数据值，提供将一个或多个位数据存储在单个存储器单元中的能力。 为了控制阈值电压，可以通过在空位内捕获电子来操纵氧空位，从空位释放被俘获的电子，移动捕获层内的空位并湮灭空位。

公开(公告)号：US20070210390A1

公开(公告)日：2007-09-13

申请号：US11714220

申请日：2007-03-06

Applicant: Sukesh Sandhu ,  Gurtej Sandhu

Inventor： Sukesh Sandhu ,  Gurtej Sandhu

IPC: H01L29/76

CPC classification number: H01L21/76232 ,  H01L21/76229

Abstract: A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of the trench, forming nitride spacers on the lined trench, and thereafter etching the silicon beneath the first trench to form a second trench area. An oxide layer is then deposited to fill the second trench. Densificiation of the isolation region is possible because the silicon is covered with nitride, and therefore will not be oxidized. Light etches are then performed to etch the oxide and nitride spacer area in the first trench region. A conventional oxide fill process can then be implemented to complete the isolation region.

Abstract translation: 形成和产生的隔离区域的方法，其允许隔离区域中的氧化物层致密化。 该方法的一个示例性实施例包括以下步骤：形成第一沟槽，在沟槽的底部和侧壁上形成氧化物层，在衬里的沟槽上形成氮化物间隔物，之后蚀刻第一沟槽下方的硅以形成第二沟槽 区。 然后沉积氧化物层以填充第二沟槽。 隔离区的密集是可能的，因为硅被氮化物覆盖，因此不会被氧化。 然后进行光蚀刻以蚀刻第一沟槽区域中的氧化物和氮化物间隔物区域。 然后可以实现常规氧化物填充过程以完成隔离区域。

公开(公告)号：US20070190463A1

公开(公告)日：2007-08-16

申请号：US11691192

申请日：2007-03-26

Applicant: Gurtej Sandhu ,  Randal Chance ,  William Rericha

Inventor： Gurtej Sandhu ,  Randal Chance ,  William Rericha

IPC: G03C5/00

CPC classification number: H01L23/50 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/1052 ,  H01L27/10894 ,  H01L2924/0002 ,  Y10S438/95 ,  Y10S438/975 ,  H01L2924/00

Abstract: Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction. In the other direction, use of photolithography and a shadowing effect caused by the relative heights of the photoresist and the narrow mask lines causes the wider mask lines to be formed with a rounded corner, thus increasing alignment tolerances in that direction by increasing the distance to a neighboring narrow mask line.

Abstract translation: 在集成电路的阵列区域中用于形成互连的窄掩模线之间的对准公差和用于在集成电路的外围形成互连的较宽的掩模线增加。 通过间距倍增形成窄屏蔽线，通过光刻法形成较宽的掩模线。 较宽的掩模线对准，使得这些线的一侧与窄线的相应侧齐平或嵌入。 较宽的掩模线的相对侧突出超过窄掩模线的对应的相对侧。 较宽的掩模线形成在具有小于窄掩模线的高度的高度的负光致抗蚀剂中。 有利地，窄掩模线可以防止掩模线在一个方向上的膨胀，从而增加该方向上的对准公差。 在另一个方向上，使用光刻法和由光致抗蚀剂和窄掩模线的相对高度引起的阴影效应导致较宽的掩模线形成有圆角，从而通过增加到该方向的距离来增加该方向上的对准公差 相邻的窄屏线。