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公开(公告)号：US11886084B2
公开(公告)日：2024-01-30
申请号：US17429676
申请日：2020-10-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Chenyang Zhang , Fuqiang Li , Ming Yang , Pengxia Liang , Jiahui Han
IPC: G02F1/1362 , G02F1/1368 , G02F1/1335 , G02F1/1343
CPC classification number: G02F1/136218 , G02F1/13439 , G02F1/13685 , G02F1/133512 , G02F1/133514 , G02F1/136227
Abstract: The disclosure provides a display substrate, a display panel and a display device. The display substrate has a display area and a peripheral area surrounding the display area, and includes: a first base; multiple pixel units in the display area and on the first base, each pixel units includes a thin film transistor and a first electrode, in each pixel unit, a second electrode of the thin film transistor is electrically coupled with the first electrode through a first via hole penetrating through an interlayer insulating layer; and an auxiliary functional layer located in the display area and on a side, away from the first base, of the first electrode; an orthographic projection of the auxiliary functional layer on the first base covers at least a part of an orthographic projection of the first via hole on the first base, and defines an active display area of each first electrode.
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62.发明授权公开(公告)号：US11837153B2
公开(公告)日：2023-12-05
申请号：US17631599
申请日：2021-03-04
Applicant: BOE Technology Group Co., Ltd.
Inventor： Ming Yang , Qi Qi , Wanzhi Chen , Lubin Shi , Fuqiang Li , Fei Wang
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2300/0408 , G09G2310/0202 , G09G2310/0264
Abstract: A light emitting substrate is provided. The light emitting substrate includes a plurality of light emitting controlling units arranged in M rows and N columns, M is an integer equal to or greater than one, N is an integer equal to or greater than one, wherein a respective one of the plurality of light emitting controlling units includes a plurality of light emitting elements arranged in J rows and I columns, J being an integer equal to or greater than one, I being an integer equal to or greater than one, a i-th column of the I columns of light emitting elements includes J rows of light emitting elements, 1≤i≤I; (M×J) number of first voltage signal lines; and (M×J) number of groups of second voltage signal lines.
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公开(公告)号：US20230215211A1
公开(公告)日：2023-07-06
申请号：US18009220
申请日：2021-05-25
Applicant: BOE Technology Group Co., Ltd.
Inventor： Changfeng Li , Xiaochuan Chen , Fuqiang Li , Liwei Liu , Hongrun Wang , Hui Zhang , Shunhang Zhang , Kai Hou , Yunsik Im , Yunping Di
IPC: G06V40/13 , G02F1/1362 , G02F1/1368
CPC classification number: G06V40/1318 , G02F1/136209 , G02F1/136222 , G02F1/1368 , G02F1/136286
Abstract: A display panel and a display device are provided. The display panel has a touch side and includes an array substrate and an opposite substrate arranged opposite to each other. The array substrate includes an image sensor array including a plurality of image sensors each including a photosensitive element configured to receive light reflected by a texture touched on the touch side for texture acquisition; the opposite substrate includes a light shielding layer including a plurality of first openings arranged in an array, and the plurality of first openings are in one-to-one correspondence with and partially overlap with the photosensitive elements of the plurality of image sensors in a direction perpendicular to a panel surface of the display panel.
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64.发明授权公开(公告)号：US11600233B2
公开(公告)日：2023-03-07
申请号：US17475358
申请日：2021-09-15
Applicant: BOE Technology Group Co., Ltd.
Inventor： Hongrun Wang , Fuqiang Li , Changfeng Li , Hui Zhang , Xue Dong
IPC: G09G3/3275 , G09G3/3266
Abstract: A display panel includes a display region and a bezel region. The bezel region includes multiple multiplexing circuits, and at least one multiplexing circuit includes m multiplexing units, 2n multiplexing control signal lines, m first multiplexing data signal lines, at least one second multiplexing data signal line and n data signal output lines. A multiplexing unit is configured to receive a gating signal of a first multiplexing data signal line based on control signals of the 2n multiplexing control signal lines in a first stage, and in a second stage, based on the gating signal, to write a first type data signal of the first multiplexing data signal line or a second type data signal of a second multiplexing data signal line into a data signal line through a data signal output line when a scan signal is input to a scan signal line.
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65.发明授权公开(公告)号：US11474633B2
公开(公告)日：2022-10-18
申请号：US17491127
申请日：2021-09-30
Applicant: BOE Technology Group Co., Ltd.
Inventor： Lubin Shi , Fuqiang Li , Fangzhen Zhang , Wei Qin
IPC: G06F3/041 , G06F3/0488 , G06F3/14 , G09G3/32 , G06F3/044
Abstract: The embodiments of the present application disclose a touch control display panel and a manufacturing method thereof, a touch control display screen and a spliced screen. The touch control display panel comprises: A substrate; A driving circuit layer, wherein the driving circuit layer comprises a driving line and a data line, a touch control row electrode and a touch control column electrode, the touch control row electrode is connected to at least one row auxiliary electrode via at least one first via hole, and each row of touch control row electrodes are connected to each other in series via the row auxiliary electrode; the touch control column electrode is connected to at least one column auxiliary electrode through at least one second via, and each column touch control column electrode is connected to each other in series through the column auxiliary electrode.
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Patent Agency Ranking
公开(公告)号：US11328652B2
公开(公告)日：2022-05-10
申请号：US16650306
申请日：2019-03-28
Inventor： Peng Liu , Bailing Liu , Fuqiang Li , Zhichong Wang , Jing Feng , Xinglong Luan
IPC: G09G5/00 , G09G3/20 , G11C19/28 , G09G3/3266 , G09G3/36
Abstract: A gate driving unit, a gate driving method, a gate driving circuit, a display panel and a display device are provided. The gate driving unit includes a start terminal, a first gate driving signal output terminal, a second gate driving signal output terminal, a pull-up control node control circuit, a pull-up node control circuit, configured to control a potential of a first pull-up node and a potential of a second pull-up node based on the potential of the pull-up control node, a first gate driving signal output circuit, a second gate driving signal output circuit, and a pull-down node control circuit, configured to control and maintain the potential of the pull-down node under the control of a third clock signal and a fourth clock signal, and control to reset the potential of the pull-down node under the control of the potential of the pull-up control node.
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公开(公告)号：US11308838B2
公开(公告)日：2022-04-19
申请号：US17051738
申请日：2020-01-21
Inventor： Zhichong Wang , Fuqiang Li , Jing Feng , Peng Liu , Xinglong Luan
Abstract: A shift register includes a first transistor, a second transistor, a pull-up node and a switch sub-circuit. A control electrode of the first transistor is connected to a signal input terminal, a first electrode of the first transistor is connected to a first voltage terminal, and a second electrode of the first transistor is connected to a first control node. A control electrode of the second transistor is connected to a reset signal terminal, a first electrode of the second transistor is connected to a second voltage terminal, and a second electrode of the second transistor is connected to the first control node. The switching sub-circuit is connected to the first control node and the pull-up node, and is configured to control a line between the first control node and the pull-up node to be closed and opened.
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公开(公告)号：US20210209988A1
公开(公告)日：2021-07-08
申请号：US16769910
申请日：2020-01-08
Inventor： Zhichong Wang , Fuqiang Li , Peng Liu , Jing Feng , Xinglong Luan
Abstract: The present disclosure provides a shift register unit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register unit includes an input sub-circuit, a discharging control sub-circuit, a discharging sub-circuit, and an output sub-circuit. The input sub-circuit is configured to transmit an input signal at an input signal terminal to a first node under control of a voltage at a second node. The discharging control sub-circuit is configured to transmit a first clock signal at a first clock signal terminal to the second node under control of a voltage at the first node. The discharging sub-circuit is configured to transmit a first constant voltage signal at a first constant voltage signal terminal to an output signal terminal under control of the voltage at the second node. The output sub-circuit is configured to transmit a second clock signal at a second clock signal terminal to the output signal terminal under control of the voltage at the first node.
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69.发明授权公开(公告)号：US10950322B2
公开(公告)日：2021-03-16
申请号：US15752790
申请日：2017-09-04
Inventor： Jun Fan , Jie Zhang , Jiguo Wang , Fuqiang Li
Abstract: A shift register unit circuit is disclosed that includes a first node control circuit, a second node control circuit, and a plurality of output circuits. Each of the plurality of output circuits is connected to a respective output terminal and provides a gate drive signal to the respective output terminal. Also disclosed are a method of driving the shift register unit circuit, a gate drive circuit, and a display apparatus.
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70.发明申请公开(公告)号：US20190189039A1
公开(公告)日：2019-06-20
申请号：US16145396
申请日：2018-09-28
Inventor： Yishan Fu , Jun Fan , Fuqiang Li , Jiguo Wang , Yue Shan , Taiyang Liu
CPC classification number: G09G3/20 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/0252 , G11C19/28
Abstract: A shift register circuit, a scan driving circuit, a display device and method for driving the scan driving circuit are provided. The shift register circuit includes: an input circuit for providing an active level for the first node upon receiving the active level of scan trigger signal; a trigger circuit for outputting the active level of scan trigger signal at the second node when first node is at the active level and a first clock signal is at first level; a locking circuit for locking the level of first node as inactive level when a first control signal is at the active level; and an output circuit for outputting a gate turn-on voltage during a period in which the second node is at an active level of the scan trigger signal, and outputting a voltage same as voltage of a second control signal during other periods other than the period.
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