PACKET MODIFICATION METHOD AND APPARATUS, COMPUTER DEVICE, AND STORAGE MEDIUM

    公开(公告)号:US20230336643A1

    公开(公告)日:2023-10-19

    申请号:US18026864

    申请日:2021-09-17

    Abstract: The present disclosure provides a packet modification method and apparatus, a computer device, and a storage medium. The method includes: dividing a field to be modified that is related to packet encapsulation information into M containers; performing instruction extraction on a very long instruction word executing a modification command, to obtain N groups of initial instructions, where 2≤N≤M; processing the N groups of initial instructions to obtain N groups of source operands and N groups of modification field configuration information; determining, according to the N groups of modification field configuration information, N containers matched with the N groups of source operands, respectively; and modifying, according to the N groups of source operands, the N matched containers, respectively.

    Method of Resetting Integrated Circuit, and Integrated Circuit

    公开(公告)号:US20230325199A1

    公开(公告)日:2023-10-12

    申请号:US18022303

    申请日:2021-08-19

    CPC classification number: G06F9/4403

    Abstract: Provided is a method of resetting an integrated circuit, including: generating, in response to a reset signal intended for a first data unit, a synchronous reset signal based on the reset signal, and outputting the synchronous reset signal to the first data unit after at least one preset period; and generating, in response to a first data signal output by the first data unit, a second data signal based on the synchronous reset signal and the first data signal, and outputting the second data signal to a second data unit. An integrated circuit is also provided.

    INTERPOSER AND CHIP PACKAGE STRUCTURE
    63.
    发明公开

    公开(公告)号:US20230290713A1

    公开(公告)日:2023-09-14

    申请号:US18011500

    申请日:2021-05-27

    CPC classification number: H01L23/49827 H01L23/49838 H01L23/58

    Abstract: Disclosed are an interposer and a chip package structure. The interposer may include: at least one signal transmission vias; at least one insulator isolation rings, one of said insulator isolation rings encircling one of said signal transmission vias; and at least one reverse-biased PN junction isolation rings, one of said reverse-biased PN junction isolation rings surrounding at least one of said insulator isolation rings, and the reverse-biased PN junction isolation ring including a semiconductor ring of a first conductivity type and a semiconductor ring of a second conductivity type from inside to outside, the semiconductor ring of the second conductivity type is connected to a bias potential.

    Information Processing Method and Device and Computer Storage Medium

    公开(公告)号:US20220321145A1

    公开(公告)日:2022-10-06

    申请号:US17413089

    申请日:2019-12-12

    Inventor: Huayong WANG

    Abstract: Provided is an information processing method. The method includes that: first data to be decoded and one or more decoding parameters of the first data are obtained; a basis matrix is determined based on the one or more decoding parameters; a decoding instruction set including a plurality of decoding instructions is determined based on the basis matrix, wherein the plurality of decoding instructions include elements in the basis matrix; and the first data is decoded based on the decoding instruction set. Further provided are an information processing device and a computer storage medium.

    Orthogonal frequency division multiplexing demodulator, demodulation method, and receiver

    公开(公告)号:US11329855B2

    公开(公告)日:2022-05-10

    申请号:US17288634

    申请日:2019-09-06

    Inventor: Jingjing Dong

    Abstract: There are provided an orthogonal frequency division multiplexing (OFDM) demodulator, a demodulation method and a receiver. The OFDM demodulator includes a phase analog-to-digital converter and a determiner, wherein the phase analog-to-digital converter is configured to acquire an OFDM analog signal, extract and quantize phase information of a modulated signal on each subcarrier in the OFDM analog signal, and output a phase quantified value corresponding to the phase information of the each subcarrier; and the determiner is configured to perform determination according to the phase quantified value, to obtain modulation information corresponding to the each subcarrier.

    Synchronization Method and Device, Synchronization System, and Computer-Readable Storage Medium

    公开(公告)号:US20220021571A1

    公开(公告)日:2022-01-20

    申请号:US17312715

    申请日:2019-12-16

    Abstract: Provided is a synchronization method, which includes: a first device periodically sends a first PSS sequence and first PDSCH control information at frequency points F1 to FN in sequence, where the first PSS sequence and the first PDSCH control information are used for a second device to detect the first PSS sequence and detect the first PDSCH control information; the first device receives signals at frequency points f1 to fM in sequence and detects a second PSS sequence; when the second PSS sequence is detected, the first device obtains second half-frame synchronization information and detects second PDSCH control information according to the second half-frame synchronization information; and when the second PDSCH control information is detected, the first device obtains second frame synchronization information and enters a synchronization state. Also provided are a synchronization device, a synchronization system, and a computer-readable storage medium.

    METHOD AND DEVICE FOR REDUCING BANDWIDTH CONSUMPTION, DISPLAY CONTROLLER, AND STORAGE MEDIUM

    公开(公告)号:US20200294475A1

    公开(公告)日:2020-09-17

    申请号:US16491579

    申请日:2017-07-25

    Abstract: Embodiments of the present disclosure disclose a method and device for reducing bandwidth consumption of a display controller. The method includes: whether image data of a current User Interface (UI) frame to be displayed is the same as image data of a previous UI frame is judged; when the image data of the current UI frame to be displayed is the same as the image data of the previous UI frame, image data in a nontransparent region except a transparent region of the previous UI frame is read; and when the image data of the current UI frame to be displayed is different from the image data of the previous UI frame, a transparent region of the current UI frame to be displayed is determined according to a preset strategy. Embodiments of the present disclosure further disclose a display controller and a computer storage medium.

    MIMO SYSTEM-BASED SIGNAL DETECTION METHOD AND DEVICE, AND STORAGE MEDIUM

    公开(公告)号:US20200059274A1

    公开(公告)日:2020-02-20

    申请号:US16487866

    申请日:2018-01-15

    Inventor: Xuetao DONG

    Abstract: Disclosed are a Multiple-Input Multiple-Output (MIMO) system-based signal detection method. The method includes: performing a scaling calculation on a first covariance matrix according to first main diagonal elements in the first covariance matrix to obtain a second covariance matrix; obtaining a whitening matrix according to the second covariance matrix; taking the whitening matrix, a vector of a receiving signal and a channel matrix as input parameters, and inputting the parameters into a mathematical model for a whitening operation and perform a whitening calculation to obtain an operation result; and detecting a transmit signal in a MIMO system according to the operation result to obtain a detection result. Also disclosed are a MIMO system-based signal detection device and a computer storage medium.

    Access method and device for random access memories, control chip and storage medium

    公开(公告)号:US10552068B2

    公开(公告)日:2020-02-04

    申请号:US15571189

    申请日:2016-06-12

    Inventor: Meng Zhang

    Abstract: Disclosed are a device and method for accessing to a RAM and a control chip. The device includes a register module configured to acquire attribute information and startup information configured by a CPU and send the startup information to a searching and matching module, and also configured to store data information successfully matched by the searching and matching module and instruct the CPU to read the data information. The searching and matching module is configured to send address information to an RAM interface module according to the startup information, and also configured to acquire the data information sent by the RAM interface module, match the data information based on the attribute information in the register module and send the data information to the register module after matching is successful. The RAM interface module is configured to read the data information from the RAM based on the address information sent by the searching and matching module and send the data information to the searching and matching module.

Patent Agency Ranking