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    PRINTED CIRCUIT BOARD CIRCUIT TEST FIXTURE WITH ADJUSTABLE DENSITY OF TEST PROBES MOUNTED THEREON
    64.
    发明申请
    PRINTED CIRCUIT BOARD CIRCUIT TEST FIXTURE WITH ADJUSTABLE DENSITY OF TEST PROBES MOUNTED THEREON 审中-公开

    公开(公告)号：US20170299632A1

    公开(公告)日：2017-10-19

    申请号：US15130982

    申请日：2016-04-17

    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

    Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

    IPC: G01R1/073 ,  G01R31/28

    CPC classification number: G01R1/07378 ,  G01R1/07328 ,  G01R31/2808

    Abstract: A printed circuit board (PCB) test fixture includes a substrate, a first insulation layer formed on the substrate, a conductor layer formed on the first insulation layer and electrically connected to the upper electrodes through at least one first connection member, a second insulation layer formed on the first insulation layer, and multiple conductive cones arranged on the second insulation layer in a matrix form. A part of the conductive cones is electrically connected to the conductor layer through at least one second connection member. The circuit layout of the conductor layer, the at least one first connection member and the at least one second connection member is employed to supply testing power to a part of the conductive cones and an adjustable arrangement of the conductive cones to enhance density of test probes upon electrical testing.

    COPPER ETCHING METHOD FOR MANUFACTURING CIRCUIT BOARD
    66.
    发明申请
    COPPER ETCHING METHOD FOR MANUFACTURING CIRCUIT BOARD 审中-公开
    用于制造电路板的铜蚀刻方法

    公开(公告)号：US20160262269A1

    公开(公告)日：2016-09-08

    申请号：US14640993

    申请日：2015-03-06

    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

    Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

    IPC: H05K3/18 ,  H05K3/06

    CPC classification number: H05K3/205 ,  H05K2201/0376 ,  H05K2203/0376

    Abstract: Disclosed is a copper etching method for manufacturing a circuit board, including steps of electroplating a metal copper support layer, coating a thermal sensitive photo resist layer, coating a photo resist layer, performing a process of pattern transfer, removing part of the photo resist layer to form a photo resist pattern, electroplating a metal copper layer to form a circuit pattern, peeling off the photo resist layer, pressing a stacked body composed of a stacked substrate and a stacked material layer onto the circuit pattern to embed the circuit pattern in the stacked material layer, removing the base layer, performing a copper etching process to removing the metal copper support layer, and removing the thermal sensitive photo resist layer to expose the circuit pattern. In particular, the circuit pattern protrudes from the stacked material layer so as to facilitate the subsequent process of forming solder balls.

    Abstract translation: 公开了一种用于制造电路板的铜蚀刻方法，包括以下步骤：电镀金属铜支撑层，涂覆热敏光致抗蚀剂层，涂覆光致抗蚀剂层，执行图案转印工艺，去除部分光致抗蚀剂层 以形成光刻胶图形，电镀金属铜层以形成电路图案，剥离光致抗蚀剂层，将由堆叠的基板和堆叠的材料层组成的堆叠体压在电路图案上，以将电路图案嵌入到 层叠材料层，去除基底层，进行铜蚀刻工艺以除去金属铜载体层，以及去除热敏光刻胶层以暴露电路图案。 特别地，电路图案从堆叠的材料层突出，以便于随后的形成焊球的工艺。

    Method of manufacturing a thin support package structure
    68.
    发明授权
    Method of manufacturing a thin support package structure 有权
    制造薄支撑包装结构的方法

    公开(公告)号：US09351409B2

    公开(公告)日：2016-05-24

    申请号：US13960123

    申请日：2013-08-06

    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

    Inventor： Hsueh-Ping Chien ,  Jun-Chung Hsu

    IPC: H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  H05K3/22

    CPC classification number: H05K3/4682 ,  H05K3/007 ,  H05K3/22 ,  H05K2201/2009 ,  H05K2203/0165 ,  H05K2203/0169 ,  H05K2203/162

    Abstract: A method of manufacturing a thin support package structure includes the steps of: preparing a support plate formed with a plurality of grooves adjacent to an outer rim thereof, forming a releasing material layer on the support plate; forming a first circuit layer on the releasing material layer so as to form a thin circuit board; forming a dielectric layer on the releasing material layer; forming a plurality of openings in the dielectric layer; forming a second circuit layer on the dielectric layer; forming connection plugs by filling the openings; forming a solder mask on the dielectric layer; forming a plurality of notches on the lower surface of the support plate to communicate with the grooves, respectively; and removing the central part of the support plate between the notches and the central part of the releasing material layer on the support plate.

    Abstract translation: 制造薄支撑包装结构的方法包括以下步骤：制备形成有与其外缘相邻的多个槽的支撑板，在支撑板上形成释放材料层; 在所述释放材料层上形成第一电路层以形成薄电路板; 在释放材料层上形成介电层; 在介电层中形成多个开口; 在所述电介质层上形成第二电路层; 通过填充开口形成连接插头; 在电介质层上形成焊料掩模; 在所述支撑板的下表面上分别形成多个凹槽以与所述凹槽连通; 并且在支撑板上的切口和释放材料层的中心部分之间移除支撑板的中心部分。

    METHOD FOR MANUFACTURING CIRCUIT BOARD BY ETCHING POLYIMIDE
    69.
    发明申请
    METHOD FOR MANUFACTURING CIRCUIT BOARD BY ETCHING POLYIMIDE 审中-公开
    通过蚀刻聚酰亚胺制造电路板的方法

    公开(公告)号：US20160081200A1

    公开(公告)日：2016-03-17

    申请号：US14487233

    申请日：2014-09-16

    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

    Inventor： CHEN-LIN WANG ,  JIUNN-CHENN LU ,  CHIH-CHANG SU

    IPC: H05K3/44 ,  H05K3/42

    CPC classification number: H05K3/243 ,  H05K3/0017 ,  H05K3/0035 ,  H05K3/281 ,  H05K2201/0154 ,  H05K2203/0588 ,  H05K2203/1572 ,  H05K2203/1581

    Abstract: A method for manufacturing circuit board includes steps of forming upper and lower copper foil layers on upper and lower surface of a PI substrate, respectively, etching the upper and lower copper foil layers to form first and second electrical circuits, attaching first and second PI coverlays to the upper and lower copper foil layers, respectively, etching the PI substrate through a PI etching process to form at least one opening exposing the lower copper foil layer, and performing a surface treatment to form a solder layer electrically connected to the electrical circuit of the lower copper foil layer for soldering electrical elements in a subsequent process. Therefore, the circuit board with double side circuit and single side assembly is obtained. The present invention do not employ the process of exposure ink, thereby simplifying the whole manufacturing procedure and greatly improving preciseness of the circuit board.

    Abstract translation: 一种制造电路板的方法，包括分别在PI基片的上表面和下表面上形成上，下铜箔层的步骤，蚀刻上下铜箔层，形成第一和第二电路，将第一和第二PI覆盖层 分别向上下铜箔层通过PI蚀刻工艺蚀刻PI衬底以形成暴露下铜箔层的至少一个开口，并进行表面处理以形成电连接到电路的电路的焊料层 用于在后续工艺中焊接电气元件的下部铜箔层。 因此，获得具有双面电路和单面组件的电路板。 本发明不采用曝光油墨的方法，从而简化了整个制造过程并大大提高了电路板的精度。

    MULTILAYER SUBSTRATE STRUCTURE FOR FINE LINE
    70.
    发明申请
    MULTILAYER SUBSTRATE STRUCTURE FOR FINE LINE 审中-公开
    精细线路的多层基板结构

    公开(公告)号：US20150282306A1

    公开(公告)日：2015-10-01

    申请号：US14225671

    申请日：2014-03-26

    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

    Inventor： Ting-Hao Lin ,  Yu-Te Lu

    IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09

    CPC classification number: H05K3/4679 ,  H05K1/116 ,  H05K2201/0376

    Abstract: A multilayer substrate structure includes a first plastic sheet, a second plastic sheet, a first circuit pattern layer, a second circuit pattern layer, and an interlayer connection pad. A first connection plug connected to the interlayer connection pad fills in a first opening of a first plastic sheet and is connected to a first connection pad of the first circuit pattern layer. A second connection plug fills a second opening of the second plastic sheet and is connected to a second connection pad of the second circuit pattern layer such that the second circuit pattern layer is electrically connected to the first circuit pattern layer via the interlayer connection pad. Therefore, even if there is little offset, it is possible to overcome the alignment tolerance and assure electrical connection between the circuit layers as desired.

    Abstract translation: 多层基板结构包括第一塑料片，第二塑料片，第一电路图案层，第二电路图案层和层间连接垫。 连接到层间连接焊盘的第一连接插头填充第一塑料片的第一开口并连接到第一电路图案层的第一连接焊盘。 第二连接插头填充第二塑料片的第二开口并且连接到第二电路图案层的第二连接焊盘，使得第二电路图案层经由层间连接焊盘电连接到第一电路图案层。 因此，即使几乎没有偏移，也可以克服对准公差，并且根据需要确保电路层之间的电连接。

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