公开(公告)号：US5970335A

公开(公告)日：1999-10-19

申请号：US797547

申请日：1997-02-07

Applicant: Mark Helm ,  Charles Dennison

Inventor： Mark Helm ,  Charles Dennison

IPC: H01L21/8238 ,  H01L21/8239

CPC classification number: H01L21/823871 ,  H01L27/1052 ,  Y10S148/123

Abstract: A semiconductor processing method of forming complementary first conductivity type doped and second conductivity type doped active regions within a semiconductor substrate includes, a) providing a semiconductor substrate; b) masking a desired first conductivity type region of the substrate while conducting second conductivity type doping into a desired second conductivity type active region of the substrate; c) providing an insulating layer over the substrate over the desired first conductivity type region and the second conductivity type doped region; d) patterning the insulating layer to provide a void therethrough to the desired first conductivity type region; e) filling the void with a first conductivity type doped polysilicon plug, the plug having a first conductivity type dopant impurity concentration of at least 1.times.10.sup.20 ions/cm.sup.3, the desired first conductivity type region having a first conductivity type dopant concentration prior to the filling step which is in the range of from 0 ions/cm.sup.3 to 1.times.10.sup.19 ions/cm.sup.3 ; and f) annealing the substrate for a period of time effective to out-diffuse first conductivity type dopant impurity from the first conductivity type doped polysilicon plug into the substrate to form the desired first conductivity type active region having a first conductivity type dopant impurity concentration of at least 1.times.10.sup.20 ions/cm.sup.3 in the substrate. Methods of forming CMOS FET transistors, and SRAM and DRAM CMOS circuitry are also disclosed.

Abstract translation: 在半导体衬底内形成互补的第一导电类型掺杂和第二导电类型掺杂有源区的半导体处理方法包括：a）提供半导体衬底; b）掩蔽所述衬底的期望的第一导电类型区域，同时将第二导电类型掺杂到所述衬底的期望的第二导电类型有源区; c）在期望的第一导电类型区域和第二导电类型掺杂区域上的衬底上方提供绝缘层; d）图案化绝缘层以提供穿过其到期望的第一导电类型区域的空隙; e）用第一导电型掺杂多晶硅插塞填充空隙，所述插塞具有至少1×10 20个离子/ cm 3的第一导电类型掺杂剂杂质浓度，所述第一导电类型区域在填充步骤之前具有第一导电类型掺杂剂浓度 其范围为0离子/ cm 3至1×10 19离子/ cm 3; 以及f）使所述衬底退火一段时间以有效地将第一导电类型的掺杂杂质从所述第一导电型掺杂多晶硅插塞扩散到所述衬底中，以形成所述第一导电类型有源区，所述第一导电类型的掺杂杂质浓度为 在衬底中至少1×1020离子/ cm3。 还公开了形成CMOS FET晶体管，以及SRAM和DRAM CMOS电路的方法。

公开(公告)号：US5844254A

公开(公告)日：1998-12-01

申请号：US858863

申请日：1997-05-19

Applicant: Monte Manning ,  Charles Dennison

Inventor： Monte Manning ,  Charles Dennison

IPC: H01L21/8244 ,  H01L27/11 ,  H01L29/76

CPC classification number: H01L27/11 ,  H01L27/1108 ,  Y10S257/903

Abstract: The disclosure includes preferred semiconductor transistor devices utilizing thin film transistors, as well as preferred methods of forming such devices. Specifically, a bottom thin film transistor gate is formed having a top surface. An insulating filler is provided adjacent the thin film transistor gate to an elevation at least as high as the thin film transistor gate top surface, and subsequently levelled to provide generally planar insulating surfaces adjacent the thin film transistor gate. The planar insulating surfaces are substantially coplanar with the thin film transistor gate top surface. A planar semiconductor thin film is then formed over the thin film transistor gate and over the adjacent planar insulating surfaces. The thin film is doped to form source and drain regions of a thin film transistor which is bottom gated by the thin film transistor gate.

Abstract translation: 本公开包括使用薄膜晶体管的优选半导体晶体管器件以及形成这种器件的优选方法。 具体地，形成具有顶表面的底部薄膜晶体管栅极。 在薄膜晶体管栅极附近提供绝缘填充物，至少与薄膜晶体管栅极顶表面一样高，并且随后平整以提供与薄膜晶体管栅极相邻的大致平面的绝缘表面。 平面绝缘表面基本上与薄膜晶体管栅极顶表面共面。 然后在薄膜晶体管栅极上方并在相邻的平面绝缘表面上形成平面半导体薄膜。 掺杂薄膜以形成薄膜晶体管的源区和漏极区，薄膜晶体管是由薄膜晶体管栅极选通的。

公开(公告)号：US5661045A

公开(公告)日：1997-08-26

申请号：US763848

申请日：1996-12-09

Applicant: Monte Manning ,  Charles Dennison ,  Howard Rhodes ,  Tyler Lowrey

Inventor： Monte Manning ,  Charles Dennison ,  Howard Rhodes ,  Tyler Lowrey

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8244 ,  H01L21/265

CPC classification number: H01L29/66659 ,  H01L21/823412 ,  H01L27/11

Abstract: A method for forming semiconductor devices includes a low energy implant for tailoring the electrical characteristics of the semiconductor devices. Using the low energy implant, narrow width devices such as access transistors in an SRAM cell, can be fabricated with a low threshold voltage (Vt). The low energy implant is performed on the active areas of a silicon substrate following field isolation and field implant. For an n-conductivity access transistor, the low energy dopant can be an n-type dopant such as phosphorus, arsenic or antimony.

Abstract translation: 用于形成半导体器件的方法包括用于调整半导体器件的电特性的低能量注入。 使用低能量注入，可以以低阈值电压（Vt）制造诸如SRAM单元中的存取晶体管的窄宽度器件。 在场隔离和场植入之后，在硅衬底的有源区域上执行低能量注入。 对于n导电性存取晶体管，低能掺杂剂可以是n型掺杂剂，例如磷，砷或锑。

公开(公告)号：US20190339585A1

公开(公告)日：2019-11-07

申请号：US16517315

申请日：2019-07-19

Applicant: John Heck ,  Harel Frish ,  Derchang Kau ,  Charles Dennison ,  Haisheng Rong ,  Jeffrey Driscoll ,  Jonathan K. Doylend ,  George A. Ghiurcan ,  Michael E. Favaro

Inventor： John Heck ,  Harel Frish ,  Derchang Kau ,  Charles Dennison ,  Haisheng Rong ,  Jeffrey Driscoll ,  Jonathan K. Doylend ,  George A. Ghiurcan ,  Michael E. Favaro

IPC: G02F1/295

Abstract: Embodiments include apparatuses, methods, and systems including a semiconductor photonic device having a substrate, a waveguide disposed above the substrate, a phase change layer disposed above the waveguide, and a heater disposed above the phase change layer. The waveguide has a modifiable refractive index based at least in part on a state of a phase change material included in the phase change layer. The phase change material of the phase change layer is in a first state of a set of states, and the waveguide has a first refractive index determined based on the first state of the phase change material. The heater is to generate heat to transform the phase change material to a second state of the set of states, and the waveguide has a second refractive index determined based on the second state of the phase change material. Other embodiments may also be described and claimed.

公开(公告)号：US08946606B1

公开(公告)日：2015-02-03

申请号：US12660490

申请日：2010-02-26

Applicant: John Charles Dennison ,  Clayton Houston Davis ,  Brian Edward Frazier

Inventor： John Charles Dennison ,  Clayton Houston Davis ,  Brian Edward Frazier

IPC: F41G7/22 ,  F41G9/00 ,  F42B15/01 ,  F41G7/00 ,  F42B15/00

CPC classification number: F41G7/2286 ,  F41G7/2246 ,  F41G7/2253 ,  F41G7/2293 ,  F42B15/01 ,  G01C21/20 ,  G01C21/3602 ,  G01S3/784 ,  G01S11/12 ,  G01S13/89 ,  G01S17/89 ,  G06T7/269 ,  G06T7/70 ,  G06T2207/10016 ,  G06T2207/30212 ,  G06T2207/30252

Abstract: Apparatus/method estimate LOS rotation, to track, approach, pursue, intercept or avoid objects. Vehicle-fixed imagers approach/recede-from objects, recording image series with background. Computations, from images exclusively, estimate rotation vs. the vehicle, applying the estimate. Preferably, recording/estimating provide proportional navigation; scan mirrors extend strapdown-sensor FOR; applying includes measuring “range rate over range”, exclusively from interimage optical flow, using results to optimize proportional-navigation loop gain; estimating includes evaluating interframe optical flow, preregistering roughly as first approximation, selecting sequence anchor points, and applying a second, finer technique developing output registration that's a coordinate translation, aligning inertial surroundings. The approximation operates optical flow with efficient embedded registration/mapping, applying a homography matrix to nearby imagery. Alternatively, inexpensive low-quality inertial sensors establish preregistration, deriving a homography matrix. When contrast in the object direction is inadequate, dual sensors yield accurate virtual imaging with an object centroid superposed into background.

Abstract translation: 仪器/方法估计LOS旋转，跟踪，接近，追踪，拦截或避免物体。 车载固定摄像机接近/离开对象，录制带有背景的影像系列。 计算，从图像专门估计旋转与车辆，应用估计。 优选地，记录/估计提供比例导航; 扫描镜延伸伸缩传感器FOR; 应用包括测量“范围速率超范围”，专门从平面图像光流，使用结果来优化比例导航环路增益; 估计包括评估帧间光流，大致预先注册为第一近似，选择序列锚点，以及应用第二更精细的技术开发作为坐标平移的输出注册，对准惯性环境。 近似运算通过有效的嵌入式注册/映射来操作光流，将单应性矩阵应用于附近的图像。 或者，廉价的低质量惯性传感器建立预注册，导出单应性矩阵。 当对象方向的对比度不足时，双传感器产生准确的虚拟成像，并将物体重心叠加到背景中。

公开(公告)号：US20070096090A1

公开(公告)日：2007-05-03

申请号：US11262246

申请日：2005-10-28

Applicant: Charles Dennison

Inventor： Charles Dennison

IPC: H01L29/18

CPC classification number: H01L45/144 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/1675

Abstract: A phase change memory may include an ovonic threshold switch formed over an ovonic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.

Abstract translation: 相变存储器可以包括在超声波存储器上形成的超声门限开关。 在一个实施例中，开关包括与下面的电极重叠的硫族化物层。 然后，由于蚀刻硫族化物层而导致的边缘损坏可以被隔离以减少漏电流。

公开(公告)号：US07196351B2

公开(公告)日：2007-03-27

申请号：US11013036

申请日：2004-12-15

Applicant: Chien Chiang ,  Charles Dennison ,  Tyler Lowrey

Inventor： Chien Chiang ,  Charles Dennison ,  Tyler Lowrey

IPC: H01L29/04 ,  H01L31/20 ,  H01L31/036 ,  H01L31/0376

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

Abstract: Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the phase changes. The heater may be coupled to an appropriate conductor.

公开(公告)号：US20060097341A1

公开(公告)日：2006-05-11

申请号：US10982295

申请日：2004-11-05

Applicant: Fabio Pellizzer ,  Charles Dennison

Inventor： Fabio Pellizzer ,  Charles Dennison

IPC: H01L29/00 ,  H01L21/477

CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: A semiconductor substrate is covered by a dielectric region. The dielectric region accommodates a memory element and a selection element forming a phase change memory cell. The memory element is formed by a resistive element and by a storage region of a phase change material extending on and in contact with the resistive element at a contact area. The selection element is formed by a switching region of chalcogenic material embedded in the dielectric region and belonging to a stack extending on the resistive element and including also the storage region. A mold region extends on top of the resistive element and delimits a trench having a substantially elongated shape. At least one portion of the storage region extends in the trench and defines a phase change memory portion over the contact area.

Abstract translation: 半导体衬底被电介质区域覆盖。 电介质区域容纳存储元件和形成相变存储单元的选择元件。 存储元件由电阻元件和在接触区域上延伸并与电阻元件接触的相变材料的存储区域形成。 选择元件由嵌入在电介质区域中的属于在电阻元件上延伸并且还包括存储区域的堆叠的金属的切换区域形成。 模具区域在电阻元件的顶部延伸并限定具有基本细长形状的沟槽。 存储区域的至少一部分在沟槽中延伸并限定了接触区域上的相变存储部分。

公开(公告)号：US20060073655A1

公开(公告)日：2006-04-06

申请号：US10948884

申请日：2004-09-24

Applicant: Charles Dennison

Inventor： Charles Dennison

IPC: H01L21/8238

CPC classification number: H01L45/142 ,  H01L27/2409 ,  H01L45/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1675

Abstract: A select device may have its threshold current reduced relative to the threshold current of a phase change memory element by providing within the select device a breakdown layer. Because the breakdown layer forms a breakdown filament along its length, the relative area between layers may be reduced, reducing the threshold current of the select device relative to that of the memory element. In addition, a stack may be formed with the select device over the memory element. The select device may be arranged so that the position of the breakdown filament may be moved inwardly relative to the etched edge to also reduce leakage current. In one embodiment, sidewall spacers may be formed on a portion of the select device.

Abstract translation: 通过在选择装置内提供击穿层，选择装置可以相对于相变存储元件的阈值电流减小其阈值电流。 因为击穿层沿其长度形成击穿细丝，所以可以减小层之间的相对面积，从而减小选择装置相对于存储元件的阈值电流。 此外，可以在存储器元件上与选择器件形成堆叠。 选择装置可以被布置成使得击穿细丝的位置可以相对于蚀刻的边缘向内移动，以减少泄漏电流。 在一个实施例中，侧壁间隔物可以形成在选择装置的一部分上。

公开(公告)号：US20060001016A1

公开(公告)日：2006-01-05

申请号：US10881664

申请日：2004-06-30

Applicant: Charles Dennison

Inventor： Charles Dennison

IPC: H01L29/02

CPC classification number: G11C13/0004 ,  G11C13/0069 ,  G11C2013/0083 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144

Abstract: A thin film phase change memory may be provided with a layer which changes between amorphous and crystalline states. The threshold voltage of that layer may be increased in a variety of fashions. As a result of the threshold increase, it is possible to transition cells, initially fabricated in the set or low resistance state, into the reset or high resistance state. In one advantageous embodiment, after such initialization and programming, the threshold voltage increase is eliminated so that the cells operate thereafter without the added threshold voltage.

Abstract translation: 薄膜相变存储器可以设置有在非晶态和晶态之间变化的层。 该层的阈值电压可以以各种方式增加。 作为门限增加的结果，可以将初始以设定或低电阻状态制造的电池转换成复位或高电阻状态。 在一个有利的实施例中，在这样的初始化和编程之后，消除阈值电压增加，使得在没有增加的阈值电压的情况下，电池工作。