BLUETOOTH AUDIO BROADCASTING SYSTEM AND RELATED MULTI-MEMBER BLUETOOTH DEVICE

    公开(公告)号:US20230370772A1

    公开(公告)日:2023-11-16

    申请号:US18359734

    申请日:2023-07-26

    CPC classification number: H04R3/00 H04M1/6066 G06F3/165 H04W4/80 H04R2420/07

    Abstract: A Bluetooth audio broadcasting system includes: an audio broadcasting device, a first Bluetooth member device, and a second Bluetooth member device. The audio broadcasting device broadcasts BLE audio packets and transmits a predetermined volume instruction to the first Bluetooth member device and the second Bluetooth member device before broadcasting the BLE audio packets. The first Bluetooth member device parses the BLE audio packets to acquire a predetermined audio data, controls a first audio playback circuit to playback the predetermined audio data, and configures an audio volume of the first audio playback circuit in advance according to the predetermined volume instruction. The second Bluetooth member device parses the BLE audio packets to acquire the predetermined audio data, controls a second audio playback circuit to playback the predetermined audio data, and configures an audio volume of the second audio playback circuit in advance according to the predetermined volume instruction.

    Firmware updating system and method

    公开(公告)号:US11803366B2

    公开(公告)日:2023-10-31

    申请号:US17231119

    申请日:2021-04-15

    Abstract: A firmware updating system and method are provided. The firmware updating method includes configuring a host to digitally sign a firmware to be updated, and configuring an electronic device to perform an authorization verification on an update tool, and only the update tool that passes the verification has an update permission. The update tool uses an encryption algorithm to encrypt the firmware to be updated that includes a digital signature. After the encryption is completed, the host sends the update tool to the electronic device through the update tool. The electronic device then uses a decryption algorithm to decrypt the received firmware to obtain the firmware to be updated including the digital signature, and write the firmware to be updated into a firmware storage area to be updated. The electronic device then verifies the digital signature in the firmware to be updated.

    MEDIA PLAYBACK METHOD FOR IMPROVING PLAYBACK RESPONSE TIME AND RELATED MEDIA PLAYBACK DEVICE

    公开(公告)号:US20230345078A1

    公开(公告)日:2023-10-26

    申请号:US18135728

    申请日:2023-04-17

    CPC classification number: H04N21/47217 H04N19/159 H04N7/013

    Abstract: A method for performing media playback on a media playback device, including: receiving a data stream to buffer the data stream in a buffer unit or to record the data stream in a storage unit; performing a parsing operation on the buffered data stream or the recorded data stream to obtain frame time and data offset corresponding to one or more intra-coded pictures of at least one audiovisual (AV) content included in the data stream, thereby to create a frame index table; in response to a playback operation, referring to the frame index table to determine a data offset associated with the playback operation; retrieving one or more data units from the buffer unit or the storage unit according to the data offset; and decoding the one or more data units for media playback.

    Analog-to-digital converter, low-dropout regulator and comparison control circuit thereof

    公开(公告)号:US11791812B2

    公开(公告)日:2023-10-17

    申请号:US17539456

    申请日:2021-12-01

    CPC classification number: H03K5/24 G05F1/575 H03K3/0377 H03M1/466

    Abstract: A comparison control circuit is adapted to analog-to-digital converters and low-dropout regulators. The comparison control circuit includes a comparator, a Schmitt trigger, a capacitor set and a logic circuit. The comparator is configured to output a comparison signal according to a first input signal and a second input signal, wherein the comparison signal is a first high voltage potential or a first low voltage potential. The Schmitt trigger is configured to output a trigger signal according to the comparison signal and a voltage potential range, wherein the voltage potential range is in a range from the first low voltage potential to the first high voltage potential. The capacitor set is configured to adjust the second input signal when being controlled. The logic circuit is configured to control the capacitor set according to the trigger signal to correspondingly adjust the second input signal.

    TRANSCEIVER CIRCUIT
    66.
    发明公开
    TRANSCEIVER CIRCUIT 审中-公开

    公开(公告)号:US20230299803A1

    公开(公告)日:2023-09-21

    申请号:US18120959

    申请日:2023-03-13

    Inventor: Yi-Chang Shih

    CPC classification number: H04B1/38 H04B1/006 H04B1/0071

    Abstract: The present invention provides a transceiver circuit including receiver circuit, wherein the receiver circuit includes a first mixer, a second mixer, a complex filter, a switch module and an ADC. The first mixer is configured to mix an input signal with a first oscillation signal to generate a first mixed signal. The second mixer is configured to mix the input signal with a second oscillation signal to generate a second mixed signal. The complex filter is configured to generate a first intermediate frequency signal and a second intermediate frequency signal according to the first mixed signal and the second mixed signal. The switch module is configured to select one of the first intermediate frequency signal and the second intermediate frequency signal to serve as an output intermediate frequency signal. The ADC is configured to perform an analog-to-digital conversion operation on the output intermediate frequency signal to generate a digital signal.

    Method and system for processing data flow with incomplete comparison process

    公开(公告)号:US11765088B2

    公开(公告)日:2023-09-19

    申请号:US17573187

    申请日:2022-01-11

    Inventor: Kuo-Cheng Lu

    CPC classification number: H04L45/7453 H04L47/20 H04L47/2475

    Abstract: A method and a system for processing a data flow with an incomplete comparison process are provided. The method is implemented by a network device that includes a flow table and a flow filter in a memory thereof. A flow analyzing module is provided for analyzing and classifying packets of an input flow, and identifying an application category to which the input flow belongs. The flow table is queried according to a result of resolving the input flow for determining whether the input flow matches any flow entry of the flow table. The flow filter is queried if the input flow fails to match any flow entry of the flow table for determining whether features of the input flow match conditions of the flow filter. The input flow is processed accordingly, without needing to copy all flows that do not match the flow entries to the flow table.

    Transmitter circuit, compensation value calibration device and method for calibrating compensation values

    公开(公告)号:US11764815B2

    公开(公告)日:2023-09-19

    申请号:US17894171

    申请日:2022-08-24

    Inventor: Tzu-Ming Kao

    CPC classification number: H04B1/0475 H04B17/11

    Abstract: A method for calibrating one or more compensation values utilized by a compensation device of a transmitter includes: obtaining a plurality of output signals which were sequentially generated by the transmitter by processing a pair of input signals according to multiple pairs of compensation values as a plurality of feedback signals, where each feedback signal corresponds to one of the multiple pairs of compensation values, determining a plurality of coefficients of a cost function according to the multiple pairs of compensation values and the feedback signals in an operation of calibration; and determining a pair of calibrated compensation values according to the coefficients and providing the pair of calibrated compensation values to the compensation device.

    Circuit and calibration method of all-digital phase-locked loop circuit

    公开(公告)号:US11764793B2

    公开(公告)日:2023-09-19

    申请号:US17699164

    申请日:2022-03-20

    Inventor: Yu-Che Yang

    CPC classification number: H03L7/0991 G04F10/005 H03L7/085 H03L2207/50

    Abstract: An all-digital phase-locked loop (ADPLL) circuit and a calibration method thereof are provided. The ADPLL circuit includes a digitally controlled oscillator (DCO) circuit, a phase detector circuit, and a calibration circuit coupled between the DCO circuit and the phase detector circuit. The DCO circuit generates a clock signal according to a frequency control signal. The phase detector circuit generates a phase error value according to a reference signal and the clock signal. More particularly, after the ADPLL circuit performs a locking operation for a period of time, the frequency control signal is tied at a locked value which is obtained when the ADPLL circuit performs the locking operation, and the calibration circuit may modify a current of at least one current source within the DCO circuit according to the phase error value.

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