公开(公告)号：US20080185571A1

公开(公告)日：2008-08-07

申请号：US11701198

申请日：2007-02-01

申请人： Thomas Happ ,  Jan Boris Philipp

发明人： Thomas Happ ,  Jan Boris Philipp

IPC分类号： H01L47/00

CPC分类号： H01L27/2463 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

摘要： An integrated circuit including a memory cell includes a vertical bipolar select device including a base and an emitter. The memory cell includes a resistive memory element coupled to the emitter and a buried metallized word line contacting the base.

摘要翻译： 包括存储单元的集成电路包括具有基极和发射极的垂直双极选择器件。 存储单元包括耦合到发射极的电阻性存储器元件和接触基极的掩埋金属化字线。

公开(公告)号：US20080185570A1

公开(公告)日：2008-08-07

申请号：US12024986

申请日：2008-02-01

申请人： Albert Wu ,  Chien-Chuan Wei

发明人： Albert Wu ,  Chien-Chuan Wei

IPC分类号： H01L45/00

CPC分类号： H01L45/144 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1675

摘要： Methods for fabricating highly compact PCM memory devices are described herein. The methods may include forming a bipolar junction transistor (BJT) structure on a substrate including creating a base of the BJT structure on the substrate and creating an emitter of the BJT structure on top of the base opposite of the substrate. A heating element may then be constructed on the emitter of the BJT structure, wherein the heating element includes a material to generate heat when provided with an electrical current from the emitter. A phase change material (PCM) cell may then be built on the heating element opposite of the BJT structure.

摘要翻译： 本文描述了用于制造高度紧凑的PCM存储器件的方法。 所述方法可以包括在衬底上形成双极结型晶体管（BJT）结构，包括在衬底上形成BJT结构的基底，并在与衬底相对的基底的顶部上形成BJT结构的发射极。 然后可以在BJT结构的发射器上构造加热元件，其中，当提供来自发射器的电流时，加热元件包括产生热量的材料。 然后可以在与BJT结构相对的加热元件上建立相变材料（PCM）单元。

公开(公告)号：US07402455B2

公开(公告)日：2008-07-22

申请号：US11156989

申请日：2005-06-20

申请人： Fabio Pellizzer ,  Agostino Pirovano

发明人： Fabio Pellizzer ,  Agostino Pirovano

IPC分类号： H01L21/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： The method forms a phase change memory cell with a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction which is transverse to said first direction. The first and second thin portions are in direct electrical contact and define a contact area having sublithographic extent. The second thin portion is formed in a slit of sublithographic dimensions. According to a first solution, oxide spacer portions are formed in a lithographic opening, delimited by a mold layer. According to a different solution, a sacrificial region is formed on top of a mold layer and is used for forming the sublithographic slit in the mold layer.

摘要翻译： 该方法形成具有电阻元件和相变材料的存储区域的相变存储单元。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区具有第二薄部，所述第二薄部在与所述第一方向横切的第二方向上具有第二亚光刻尺寸。 第一和第二薄部分是直接电接触并限定具有亚光刻范围的接触区域。 第二薄部分形成在亚光刻尺寸的狭缝中。 根据第一种解决方案，氧化物间隔物部分形成在由模具层限定的光刻开口中。 根据不同的解决方案，牺牲区域形成在模具层的顶部上，并用于在模具层中形成亚光刻缝。

公开(公告)号：US20080121863A1

公开(公告)日：2008-05-29

申请号：US11753528

申请日：2007-05-24

申请人： Wei-Su CHEN

发明人： Wei-Su CHEN

IPC分类号： H01L45/00

CPC分类号： G11C13/0004 ,  H01L27/2409 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1691

摘要： A phase change memory device is provided. The phase change memory device includes a substrate comprising a stacked structure. The stacked structure comprises a plurality of insulating layers and conductive layers. Any two of the conductive layers are spaced apart by one of the conductive layers. A first electrode structure with a first sidewall and a second sidewall is formed on the stacked structure. A plurality of heating electrodes is placed on the conductive layers and adjacent to the first sidewall and the second sidewall of the first electrode structure. A pair of phase change material spacers is placed on the first sidewall and the second sidewall of the first electrode structure. The phase change material sidewalls cover the plurality of heating electrodes.

摘要翻译： 提供了相变存储器件。 相变存储器件包括包括堆叠结构的衬底。 堆叠结构包括多个绝缘层和导电层。 导电层中的任何两个由一个导电层隔开。 具有第一侧壁和第二侧壁的第一电极结构形成在堆叠结构上。 多个加热电极放置在导电层上并与第一电极结构的第一侧壁和第二侧壁相邻。 一对相变材料间隔物被放置在第一电极结构的第一侧壁和第二侧壁上。 相变材料侧壁覆盖多个加热电极。

公开(公告)号：US07372166B2

公开(公告)日：2008-05-13

申请号：US11258340

申请日：2005-10-24

申请人： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

发明人： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

IPC分类号： H01L23/48

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

摘要翻译： 电子半导体器件具有在第一导电区域和第二导电区域之间的亚光刻接触面积。 第一导电区域是杯状的并且具有垂直壁，其在顶部平面图中沿着细长形状的封闭线延伸。 第一导电区域的一个壁形成第一薄部分并且具有在第一方向上的第一尺寸。 第二导电区域具有第二薄部分，该第二薄部分具有横向于第一尺寸的第二方向的第二亚光刻尺寸。 第一和第二导电区域在其薄部分处直接电接触并形成亚光刻接触区域。 细长形状选择在第一方向上伸长的矩形和椭圆形之间。 因此，即使在限定导电区域的掩模之间存在小的不对准的情况下，接触区域的尺寸也保持近似恒定。

公开(公告)号：US07227171B2

公开(公告)日：2007-06-05

申请号：US10313991

申请日：2002-12-05

申请人： Roberto Bez ,  Fabio Pellizzer ,  Caterina Riva ,  Romina Zonca

发明人： Roberto Bez ,  Fabio Pellizzer ,  Caterina Riva ,  Romina Zonca

IPC分类号： H01L29/04

CPC分类号： G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691 ,  Y10S438/947

摘要： A contact structure, including a first conducting region having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region having a second thin portion with a second sublithographic dimension in a second direction transverse to said first direction; the first and second thin portions being in direct electrical contact and defining a contact area having a sublithographic extension. The thin portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer; the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic opening that is used to etch a mold opening in a mold layer and filling the mold opening.

摘要翻译： 一种接触结构，包括：第一导电区域，具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 第二导电区域，具有第二薄部分，具有横向于所述第一方向的第二方向的第二亚光刻尺寸; 第一和第二薄部分直接电接触并且限定具有亚光刻延伸部的接触区域。 使用沉积代替光刻获得薄部分：第一薄部分被放置在第一介电层中的开口的壁上; 通过在第一限定层的垂直壁上去除牺牲区域，在牺牲区域的自由侧上取代第二限定层，去除牺牲区域以形成用于蚀刻模具的亚光刻开口来获得第二薄部分 在模具层中开口并填充模具开口。

公开(公告)号：US07220983B2

公开(公告)日：2007-05-22

申请号：US11009365

申请日：2004-12-09

申请人： Hsiang Lan Lung

发明人： Hsiang Lan Lung

IPC分类号： H01L47/00

CPC分类号： H01L27/2445 ,  H01L27/2418 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144

摘要： The invention relates to a novel memory cell structure and process to fabricate chalcogenide phase change memory. More particularly, it produces a small cross-sectional area of a chalcogenide-electrode contact part of the phase change memory, which affects the current/power requirement of the chalcogenide memory. Particular aspects of the present invention are described in the claims, specification and drawings.

摘要翻译： 本发明涉及一种新型的存储单元结构和制造硫族化物相变存储器的方法。 更具体地，它产生相变存储器的硫族化物 - 电极接触部分的小截面面积，其影响硫族化物存储器的电流/功率需求。 在权利要求书，说明书和附图中描述了本发明的特定方面。

公开(公告)号：US07135756B2

公开(公告)日：2006-11-14

申请号：US10680727

申请日：2003-10-07

申请人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

发明人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

IPC分类号： H01L27/102

CPC分类号： H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

摘要： A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

摘要翻译： 单元阵列由多个单元形成，每个单元包括选择双极晶体管和存储组件。 电池阵列形成在包括P型共用集电极区域的主体中; 多个N型基极区，覆盖在公共集电极区域上; 在基区中形成多个P型发射极区; 以及形成在所述基极区域中的多个N型基极接触区域和比所述基极区域更高的掺杂水平的基极接触区域，其中每个基极区域由至少两个相邻的双极晶体管共享。

公开(公告)号：US20060249369A1

公开(公告)日：2006-11-09

申请号：US11398849

申请日：2006-04-05

申请人： Maria Marangon ,  Paola Besana ,  Raimondo Cecchini ,  Mauro Tresoldi

发明人： Maria Marangon ,  Paola Besana ,  Raimondo Cecchini ,  Mauro Tresoldi

IPC分类号： C23C14/32 ,  C23C14/00

CPC分类号： H01L27/2445 ,  C23C14/046 ,  C23C14/0623 ,  H01J37/3408 ,  H01J37/3447 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1625

摘要： A method for depositing a chalcogenide layer in a phase change memory, whereby a chalcogenide layer is deposited by physical vapor deposition in a deposition chamber, having a collimator. The collimator is formed by a holed disk arranged in a deposition area delimited by the chamber walls and the chamber cover. The target is biased by a pulsed voltage to avoid charging and arching. The method is used to manufacture a phase change memory cell, whereby a resistive heater element is formed in a dielectric layer, a mold layer is formed over the dielectric layer; an aperture is formed in the mold layer over the resistive heater element; a chalcogenide layer is conformally deposited in the aperture to define a phase change portion; and a select element is formed in electrical contact with the phase change portion.

摘要翻译： 一种用于在相变存储器中沉积硫族化物层的方法，由此通过物理气相沉积在具有准直仪的沉积室中沉积硫族化物层。 准直器由布置在由室壁和室盖限定的沉积区域中的孔形成。 目标被脉冲电压偏置以避免充电和拱起。 该方法用于制造相变存储单元，由此在电介质层中形成电阻加热元件，在电介质层上形成模层; 在电阻加热器元件上的模具层中形成孔; 在孔中共形沉积硫属化物层以限定相变部分; 并且选择元件形成为与相变部分电接触。

公开(公告)号：US06972430B2

公开(公告)日：2005-12-06

申请号：US10371154

申请日：2003-02-20

申请人： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

发明人： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

IPC分类号： G11C11/56 ,  H01L27/24 ,  H01L45/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

摘要翻译： 电子半导体器件具有在第一导电区域和第二导电区域之间的亚光刻接触面积。 第一导电区域是杯状的并且具有垂直壁，其在顶部平面图中沿着细长形状的封闭线延伸。 第一导电区域的一个壁形成第一薄部分并且具有在第一方向上的第一尺寸。 第二导电区域具有第二薄部分，该第二薄部分具有横向于第一尺寸的第二方向的第二亚光刻尺寸。 第一和第二导电区域在其薄部分处直接电接触并形成亚光刻接触区域。 细长形状选择在第一方向上伸长的矩形和椭圆形之间。 因此，即使在限定导电区域的掩模之间存在小的不对准的情况下，接触区域的尺寸也保持近似恒定。