公开(公告)号：US07889590B2

公开(公告)日：2011-02-15

申请号：US12611280

申请日：2009-11-03

Applicant: Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

Inventor： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

IPC: G11C8/00

CPC classification number: G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities.

公开(公告)号：US20100329029A1

公开(公告)日：2010-12-30

申请号：US12792071

申请日：2010-06-02

Applicant: Sung-Won Yun ,  Oh-Suk Kwon

Inventor： Sung-Won Yun ,  Oh-Suk Kwon

IPC: G11C16/06 ,  G11C7/10 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14

Abstract: A page buffer includes a sense latch, a data latch and a page buffer controller. The sense latch is connected to a bit line, and is configured to set stored data in response to a sense latch control signal, and to change the stored data in response to a signal applied to the bit line in a data verification operation. The data latch is configured to store multi-bit data to be programmed in a program operation, and to set stored data in response to a data latch control signal in the data verification operation. The page buffer controller is configured to control the bit line in accordance with the multi-bit data stored in the data latch in the program operation, and to output the sense latch control signal and the data latch control signal in accordance with the multi-bit data stored in the data latch in response to a control signal in the data verification operation.

Abstract translation: 页面缓冲器包括检测锁存器，数据锁存器和页面缓冲器控制器。 感测锁存器连接到位线，并且被配置为响应于感测锁存控制信号设置存储的数据，并且响应于在数据验证操作中施加到位线的信号来改变存储的数据。 数据锁存器被配置为存储要在编程操作中编程的多位数据，并且在数据验证操作中响应于数据锁存控制信号来设置存储的数据。 页缓冲器控制器被配置为在编程操作中根据存储在数据锁存器中的多位数据来控制位线，并且根据多位输出读出锁存控制信号和数据锁存控制信号 响应于数据验证操作中的控制信号而存储在数据锁存器中的数据。

公开(公告)号：US07830725B2

公开(公告)日：2010-11-09

申请号：US12130981

申请日：2008-05-30

Applicant: Se Chun Park ,  Jong Hyun Wang ,  Yu Jong Noh

Inventor： Se Chun Park ,  Jong Hyun Wang ,  Yu Jong Noh

IPC: G11C7/10

CPC classification number: G11C16/10 ,  G11C2216/14

Abstract: A page buffer includes a first ground voltage supply unit for applying a ground voltage to first and second registers according to a level of a sense node, and a second ground voltage supply unit for applying the ground voltage to the first and second registers irrespective of a level of the sense node. A method of programming a non-volatile memory device includes storing a high-level data in a first node of a first register of a plurality of page buffers, precharging a sense node with a high level, resetting the data stored in the first node of the first register according to a voltage level of the sense node, precharging the sense node with a high level, storing external data in the first node according to a voltage level of the sense node, and performing a program operation according to the data stored in the first node.

Abstract translation: 页面缓冲器包括用于根据感测节点的电平将接地电压施加到第一和第二寄存器的第一接地电压供应单元和用于将接地电压施加到第一和第二寄存器的第二接地电压供应单元，而不管 感知节点的级别。 一种编程非易失性存储器件的方法包括将高电平数据存储在多个页缓冲器的第一寄存器的第一节点中，对具有高电平的感测节点进行预充电，将存储在第一节点中的数据重置 所述第一寄存器根据所述感测节点的电压电平，对所述感测节点进行高电平预充电，根据所述感测节点的电压电平将外部数据存储在所述第一节点中，并且根据存储在所述感测节点中的数据进行编程操作 第一个节点。

公开(公告)号：US20100277980A1

公开(公告)日：2010-11-04

申请号：US12837595

申请日：2010-07-16

Applicant: Noboru SHIBATA ,  Tomoharu TANAKA

Inventor： Noboru SHIBATA ,  Tomoharu TANAKA

IPC: G11C16/04

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5646 ,  G11C2211/5648 ,  G11C2216/14

Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.

Abstract translation: 数据存储电路以一一对应的方式连接到位线。 写电路将第一页上的数据写入由字线同时选择的多个第一存储单元。 此后，写电路将第二页上的数据写入多个第一存储单元。 然后，写入电路将第一和第二页面上的数据写入与位线方向相邻的第一存储单元的第二存储单元。

公开(公告)号：US07826276B2

公开(公告)日：2010-11-02

申请号：US12003381

申请日：2007-12-21

Applicant: Jae-Woo Park ,  Bong-soon Lim

Inventor： Jae-Woo Park ,  Bong-soon Lim

IPC: G11C7/10

CPC classification number: G11C16/10 ,  G11C16/3454 ,  G11C2216/14

Abstract: Provided are a non-volatile memory device in which time required for programming may be saved, and a method of driving the same. The non-volatile memory device may include a memory cell array with a plurality of memory cells; an input/output buffer having a storage unit that stores data and indicator bits representing information regarding the data; a data scanning unit that receives the stored data from the input/output buffer in units of scanning, and that scans the received data, the received data being selectively programmed in the memory cells according to a result of scanning the data; and/or a control logic unit that controls the data stored in the input/output buffer in units of scanning to be selectively supplied to the data scanning unit based on the states of the indicator bits.

Abstract translation: 提供了可以节省编程所需的时间的非易失性存储器件及其驱动方法。 非易失性存储器件可以包括具有多个存储单元的存储单元阵列; 具有存储单元的输入/输出缓冲器，该存储单元存储表示关于数据的信息的数据和指示符位; 数据扫描单元，其以扫描为单位从输入/输出缓冲器接收存储的数据，并且根据扫描数据的结果扫描接收到的数据，该接收数据被选择性地编程在存储器单元中; 和/或控制逻辑单元，其基于指示符位的状态，以扫描为单位控制存储在输入/输出缓冲器中的数据以选择性地提供给数据扫描单元。

公开(公告)号：US20100214849A1

公开(公告)日：2010-08-26

申请号：US12647725

申请日：2009-12-28

Applicant: Hyun Jong Jin ,  Jin Haeng Lee

Inventor： Hyun Jong Jin ,  Jin Haeng Lee

IPC: G11C16/06 ,  G11C7/10

CPC classification number: G11C7/1033 ,  G11C7/065 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

Abstract: The page buffer of a nonvolatile memory device utilizing a double verification method using first and second verification voltages when performing a program verification operation includes a first latch unit including a first latch configured to store input data and results of a program operation and a first verification operation using the first verification voltage, and a second latch unit including a second latch configured to have a higher latch trip point than the first latch and to store a result of a second verification operation using the second verification voltage, which is less than the first verification voltage, when the first verification operation is performed.

Abstract translation: 当执行程序验证操作时，利用使用第一和第二验证电压的双重验证方法的非易失性存储器件的页面缓冲器包括第一锁存单元，其包括第一锁存器，其被配置为存储输入数据以及程序操作和第一验证操作的结果 使用第一验证电压，以及包括配置为具有比第一锁存器更高的锁存跳变点的第二锁存器的第二锁存单元，并且使用小于第一验证电压的第二验证电压存储第二验证操作的结果 当执行第一验证操作时。

公开(公告)号：US20100027348A1

公开(公告)日：2010-02-04

申请号：US12493317

申请日：2009-06-29

Applicant: Ju In Kim

Inventor： Ju In Kim

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C16/3454 ,  G11C2216/14

Abstract: A program method of a flash memory device includes inputting a first data and a second data to a page buffer coupled to memory cells including an even page and an odd page, pre-programming a first memory cell of the odd page using the first data, programming a second memory cell of the even page using the second data, and programming the pre-programmed first memory cell using the first data.

Abstract translation: 闪速存储装置的编程方法包括：将第一数据和第二数据输入到耦合到包括偶数页和奇数页的存储单元的页缓冲器，使用第一数据对奇数页的第一存储单元进行预编程， 使用第二数据编程偶数页面的第二存储器单元，以及使用第一数据对预编程的第一存储器单元进行编程。

公开(公告)号：US20090290418A1

公开(公告)日：2009-11-26

申请号：US12469346

申请日：2009-05-20

Applicant: Jung Chul HAN

Inventor： Jung Chul HAN

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14

Abstract: A method of verifying a program operation in a non-volatile memory device includes performing a program operation, verifying whether or not each of a plurality of program target memory cells is programmed to a voltage higher than a verifying voltage, counting a number of fail status bits in response to determining that a fail status memory cell is not programmed with a voltage higher than the verifying voltage based on the verified result, and setting data so that a plurality of page buffers each output a pass signal when the number of the fail status bits is smaller than a number of error correction code (ECC) processing bits.

Abstract translation: 一种验证非易失性存储器件中的程序操作的方法包括执行程序操作，验证多个程序目标存储器单元中的每一个是否被编程为高于验证电压的电压，对故障状态数进行计数 响应于基于验证结果确定故障状态存储单元未被编程为具有高于验证电压的电压的位，并且设置数据使得当故障状态的数量时多个页缓冲器输出通过信号 比特小于多个纠错码（ECC）处理比特。

公开(公告)号：US20090273982A1

公开(公告)日：2009-11-05

申请号：US12499136

申请日：2009-07-08

Applicant: Tokumasa HARA

Inventor： Tokumasa HARA

IPC: G11C16/06 ,  G11C7/10 ,  G11C8/00

CPC classification number: G11C16/10 ,  G11C16/3454 ,  G11C2216/14

Abstract: A semiconductor memory device includes an output buffer which outputs an enable signal which makes an external memory device operable, an address buffer which generates an address at which data is held in the external memory device, an input buffer which receives the data held at the address from the external memory device, and a write data buffer which holds the data received by the input buffer, and writes the data in a plurality of memory cells at once. Whenever the write data buffer writes data, the input buffer receives, from the external memory, the data having a size which is written in the memory cells at once.

Abstract translation: 半导体存储器件包括：输出缓冲器，其输出使外部存储器件可操作的使能信号，产生数据保存在外部存储器件中的地址的地址缓冲器;接收保持在地址的数据的输入缓冲器 以及写入数据缓冲器，其保存由输入缓冲器接收到的数据，并将数据一次写入多个存储单元。 每当写入数据缓冲器写入数据时，输入缓冲器从外部存储器接收一次具有写入存储器单元的大小的数据。

公开(公告)号：US07586785B2

公开(公告)日：2009-09-08

申请号：US12020981

申请日：2008-01-28

Applicant: Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura

Inventor： Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura

IPC: G11C16/04

CPC classification number: G11C16/105 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/102 ,  G11C16/26 ,  G11C2216/14

Abstract: A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write to the memory cell array, and a control circuit for executing a series of copy write operations in such a manner that a data output operation of from the data read/write circuit to outside of a chip and a data write operation of from the data read/write circuit to the memory cell array are overlapped each other, the copy write operation including reading data at a certain address of the memory cell array into the data read/write circuit, outputting read data held in the read/write circuit to outside of the chip and writing write data into another address of the memory cell array, the write data being a modified version of the read data held in the data read/write circuit as externally created outside the chip.

Abstract translation: 一种非易失性半导体存储器件包括其中布置有电可重写非易失性存储器单元的存储单元阵列，用于执行存储单元阵列的存储单元选择的地址选择器电路，布置成执行数据读取的数据读/写电路 的存储单元阵列和写入存储单元阵列的数据;以及控制电路，用于执行一系列复制写入操作，使得从数据读/写电路到芯片外部的数据输出操作和 从数据读/写电路到存储单元阵列的数据写入操作彼此重叠，复制写操作包括将存储单元阵列的特定地址处的数据读入数据读/写电路，输出保持在 读/写电路到芯片外部，并将写入数据写入存储单元阵列的另一个地址，写数据是保存在数据读/写中的读数据的修改版本 ite电路在芯片外部外部创建。