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    Enhanced apparatus for binary quotient, binary product, binary sum and binary difference generation
    51.
    发明授权
    Enhanced apparatus for binary quotient, binary product, binary sum and binary difference generation 失效
    二进制商，二进制和二进制差分生成的增强型设备

    公开(公告)号：US4025773A

    公开(公告)日：1977-05-24

    申请号：US639516

    申请日：1975-12-15

    Applicant: Walter Scott Bennett

    Inventor： Walter Scott Bennett

    IPC: G06F7/52

    CPC classification number: G06F7/5272 ,  G06F7/535 ,  G06F2207/3852 ,  G06F2207/5353 ,  G06F2207/5356

    Abstract: Three modular arrays structured from a common module are connected together a first way to form a binary quotient by successive approximations, or a second way to form a binary product. Any one of the three modular arrays may be used to add or subtract two binary numbers. To divide, one array is utilized to effectively form the reciprocal of the binary divisor, most significant bit first, by successive approximation. Control circuitry, including a carry detector, dictates the formation of the shift and add sequence that effectively represents the reciprocal of the divisor by controlling the positioning of the divisor before each addition step so that the product is a series of binary ones. The add and shift sequence utilized to generate the series of binary ones, as it is evolving, is also being utilized to manipulate the dividend, thereby forming the quotient, most significant bit first. In effect, the dividend is being multiplied by the reciprocal of the divisor so as to form an approximate product of the dividend and reciprocal of the divisor, most significant bit first. This product is actually an increasingly precise approximation of the quotient of the dividend and divisor. The binary product of two numbers is formed, most significant bit first, by manipulating the multiplicand according to an add and shift sequence determined by use of the multiplier.

    Abstract translation: 由公共模块构成的三个模块化阵列通过逐次逼近形成二进制商的第一种方式连接在一起，或者形成二进制产品的第二种方法。 三个模块阵列中的任何一个可用于加或减两个二进制数。 为了划分，利用一个阵列通过逐次近似有效地形成二进制除数的倒数，最高有效位。 包括进位检测器的控制电路决定了通过在每个加法步骤之前控制除数的位置使得该乘积成为一系列二进制的方法，来形成有效地表示除数的倒数的移位和加法序列。 用于生成二进制序列的加法和移位序列随着其进化，也被用于操纵分红，从而形成商，最重要的是位。 实际上，红利乘以除数的倒数，从而形成除数的近似乘积和最大有效位。 这个产品实际上是一个越来越精确的近似股息和除数的商。 通过根据通过使用乘法器确定的加法和移位序列来操纵被乘数，形成两个数字的二进制积，最高有效位。

    Apparatus and method for serial-parallel binary multiplication
    52.
    发明授权
    Apparatus and method for serial-parallel binary multiplication 失效
    用于串并行二进制多路复用的装置和方法

    公开(公告)号：US3816732A

    公开(公告)日：1974-06-11

    申请号：US34610873

    申请日：1973-03-29

    Applicant: ROCKLAND SYSTEMS CORP

    Inventor： JACKSON L

    IPC: G06F7/52 ,  G06F7/39

    CPC classification number: G06F7/5272 ,  G06F7/49947

    Abstract: The bits of the multiplier are multiplied by sequential bits of the multiplicand in ascending order of significance. These sequential products are supplied to a parallel adder, where each bit is added to the delayed sum of the preceding operation of the next higher bit in order of significance, including the carry bit as the most significant. After k bits of multiplicand have been used, truncated or rounded output becomes available at the output of the least significant stage of the adder. During the bit interval of the last bit of the multiplicand the outputs of the adder are loaded into a parallel input series output shift register, after which the remaining bits of the product are taken from the output of the shift register, the delayed flipflops associated with the adder are cleared and the adder begins to operate on the next multiplication while the shift register is unloading.

    Abstract translation: 乘法器的位以有效数字的升序乘以被乘数的顺序位。 这些顺序产品被提供给并行加法器，其中每个比特按照重要性的顺序被加到下一较高比特的前一个操作的延迟和，包括进位比特最高。 在使用被乘数的k位之后，截断或舍入的输出在加法器的最低有效级的输出端可用。 在被乘数的最后一位的比特间隔期间，加法器的输出被加载到并行输入串行输出移位寄存器中，之后产品的剩余位取自移位寄存器的输出，延迟的触发器与 当移位寄存器卸载时，加法器被清零，加法器开始在下一个乘法运算。

    System and method providing hierarchical cache for big data applications
    60.
    发明授权
    System and method providing hierarchical cache for big data applications 有权
    为大数据应用提供分层缓存的系统和方法

    公开(公告)号：US09083725B2

    公开(公告)日：2015-07-14

    申请号：US14531171

    申请日：2014-11-03

    Applicant: Fred Korangy ,  Hamed Ghasemzadeh ,  Mohsen Arjmandi ,  Reza Azmi

    Inventor： Fred Korangy ,  Hamed Ghasemzadeh ,  Mohsen Arjmandi ,  Reza Azmi

    IPC: G06F15/16 ,  H04L29/08 ,  G06F7/527 ,  G06F7/78

    CPC classification number: H04L67/1097 ,  G06F7/5272 ,  G06F7/785 ,  H04L67/1095

    Abstract: The embodiments herein develop a system for providing hierarchical cache for big data processing. The system comprises a caching layer, a plurality of actors in communication with the caching layer, a machine hosting the plurality of actors, a plurality of replication channels in communication with the plurality of actors, a predefined ring structure. The caching layer is a chain of memory and storage capacity elements, configured to store a data from the input stream. The plurality of actors is configured to replicate the input data stream and forward the replicated data to the caching layer. The replication channels are configured to forward the replicated data from a particular actor to another actor. The predefined ring structure maps the input data to the replica actors.

    Abstract translation: 本文的实施例开发了一种用于为大数据处理提供分层缓存的系统。 该系统包括缓存层，与缓存层通信的多个角色，承载多个角色的机器，与多个角色通信的多个复制频道，预定义的环形结构。 缓存层是存储器和存储容量元件链，被配置为存储来自输入流的数据。 多个演员被配置为复制输入数据流并将复制的数据转发到缓存层。 复制通道配置为将复制数据从特定演员转发到另一个演员。 预定义的环结构将输入数据映射到副本演员。

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