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公开(公告)号：US3816732A
公开(公告)日：1974-06-11
申请号：US34610873
申请日：1973-03-29
Applicant: ROCKLAND SYSTEMS CORP
Inventor： JACKSON L
CPC classification number: G06F7/5272 , G06F7/49947
Abstract: The bits of the multiplier are multiplied by sequential bits of the multiplicand in ascending order of significance. These sequential products are supplied to a parallel adder, where each bit is added to the delayed sum of the preceding operation of the next higher bit in order of significance, including the carry bit as the most significant. After k bits of multiplicand have been used, truncated or rounded output becomes available at the output of the least significant stage of the adder. During the bit interval of the last bit of the multiplicand the outputs of the adder are loaded into a parallel input series output shift register, after which the remaining bits of the product are taken from the output of the shift register, the delayed flipflops associated with the adder are cleared and the adder begins to operate on the next multiplication while the shift register is unloading.
Abstract translation: 乘法器的位以有效数字的升序乘以被乘数的顺序位。 这些顺序产品被提供给并行加法器，其中每个比特按照重要性的顺序被加到下一较高比特的前一个操作的延迟和，包括进位比特最高。 在使用被乘数的k位之后，截断或舍入的输出在加法器的最低有效级的输出端可用。 在被乘数的最后一位的比特间隔期间，加法器的输出被加载到并行输入串行输出移位寄存器中，之后产品的剩余位取自移位寄存器的输出，延迟的触发器与 当移位寄存器卸载时，加法器被清零，加法器开始在下一个乘法运算。
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2.发明授权
公开(公告)号：US3808370A
公开(公告)日：1974-04-30
申请号：US27906472
申请日：1972-08-09
Applicant: ROCKLAND SYSTEMS CORP
Inventor： JACKSON L , BERTRAND J
CPC classification number: H03H21/0012 , G01R23/00 , G10L19/02 , G10L25/93 , H03H17/06
Abstract: An adaptive filter system for determining characteristics of an electrical input signal, such as resonant frequencies, antiresonant frequencies, etc. which includes a plurality of antiresonance circuits and/or resonance circuits coupled to an input signal, means for developing indicator signals indicate the deviation of the anti-resonant and/or resonant frequencies of the circuits from the anti-resonant and/or resonant frequencies of the input signal, and means for cross-correlating the output from at least one of the circuits with the indicator signals, and for generating correction signals as a function of the crosscorrelation. The correction signals are fed to the circuits to vary the anti-resonant and/or resonant frequencies thereof so that the frequencies correspond to the respective resonant and/or anti-resonant frequencies in the input signal.
Abstract translation: 一种用于确定诸如谐振频率，反谐振频率等的电输入信号的特性的自适应滤波器系统，其包括耦合到输入信号的多个反谐振电路和/或谐振电路，用于开发指示符信号的装置 指示电路的反谐振和/或谐振频率与输入信号的反谐振和/或谐振频率的偏差，以及用于将来自至少一个电路的输出与指示符信号互相关的装置 并且用于产生作为互相关函数的校正信号。 校正信号被馈送到电路以改变其反谐振和/或谐振频率，使得频率对应于输入信号中的相应谐振和/或反谐振频率。
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公开(公告)号：US3735269A
公开(公告)日：1973-05-22
申请号：US3735269D
申请日：1971-10-29
Applicant: ROCKLAND SYSTEMS CORP
Inventor： JACKSON L
CPC classification number: G06F1/0353
Abstract: A digital frequency synthesizer using modulo 10N accumulator means for receiving signals corresponding to a predetermined frequency output and for successively generating signals corresponding to addresses in a storage means, each of the addresses corresponding to a storage location which stores digital values corresponding to at least the magnitude of a plurality of digital samples of the output signal from the synthesizer. A digital-to-analog converter converts the output of the storage means into a step-type waveform which is passed through a low pass filter to generate a smooth output waveform from the system. In order to reduce the size of the required storage device, sign and quadrature symmetry may be taken advantage of by making use of the redundancy of the magnitude of values in a sinusoidal signal generator.
Abstract translation: 一种使用模10N累加器装置的数字频率合成器，用于接收对应于预定频率输出的信号，并且用于连续产生对应于存储装置中的地址的信号，每个地址对应于存储对应于至少大小的数字值的存储位置 来自合成器的输出信号的多个数字样本。 数模转换器将存储装置的输出转换成阶跃型波形，该波形通过低通滤波器以从系统产生平稳的输出波形。 为了减小所需的存储设备的尺寸，可以通过利用正弦信号发生器中的值的大小的冗余来利用符号和正交对称性。
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