公开(公告)号：US5931915A

公开(公告)日：1999-08-03

申请号：US856619

申请日：1997-05-13

申请人： Alan F. Benner ,  Michael Grassi

发明人： Alan F. Benner ,  Michael Grassi

IPC分类号： H04L12/54 ,  G06F15/173 ,  G06F15/163

CPC分类号： G06F15/17368

摘要： A message-passing protocol for accommodating early arrival messages passed between source and destination nodes in a computer system with a plurality of asynchronous computing nodes interconnected by bidirectional asynchronous communications channels. The protocol includes transmitting the message from sender to receiver without waiting for a request for the message from the receiver; determining at the receiver if a receive buffer has been posted for the message; and if the receive buffer has not been posted for the message, then either truncating the message by storing its message header in an early arrival queue at the receiver and discarding its data or allocating a temporary receive buffer at the receiver to hold the message data. Upon the receiver being ready to post a receive buffer for an early arrival message, the receiver checks the early arrival queue for the corresponding message header, and if the message header is in the early arrival queue and the message data has been discarded, then the receiver sends a pull request to the sender to retransmit the message to the receiver.

摘要翻译： 一种消息传递协议，用于容纳在具有通过双向异步通信信道互连的多个异步计算节点的计算机系统中的源节点与目的节点之间传递的早到信息。 该协议包括从发送方发送消息到接收方，而不等待来自接收方的消息请求; 在接收器处确定是否已经为消息发布接收缓冲器; 并且如果接收缓冲器尚未被发送给消息，则通过将消息头部存储在接收器的早期到达队列中并且丢弃其数据或者在接收器处分配临时接收缓冲器来保存消息数据来截断该消息。 在接收器准备好发送用于早期到达消息的接收缓冲器的情况下，接收机检查相应消息报头的早期到达队列，并且如果消息报头处于早期到达队列中并且消息数据已被丢弃，则 接收方向发送方发送拉取请求，以将消息重发到接收方。

公开(公告)号：US5870619A

公开(公告)日：1999-02-09

申请号：US841007

申请日：1997-04-29

申请人： Paul Amba Wilkinson ,  James Warren Dieffenderfer ,  Peter Michael Kogge ,  Nicholas Jerome Schoonover

发明人： Paul Amba Wilkinson ,  James Warren Dieffenderfer ,  Peter Michael Kogge ,  Nicholas Jerome Schoonover

IPC分类号： G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F9/3885 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F7/483 ,  G06F9/30 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/38 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3889 ,  G06F9/3891

摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

公开(公告)号：US5826049A

公开(公告)日：1998-10-20

申请号：US916630

申请日：1992-07-22

申请人： Yasuhiro Ogata ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Shinichi Shutoh ,  Tatsuo Higuchi ,  Shigeo Takeuchi ,  Taturu Toba ,  Teruo Tanaka

发明人： Yasuhiro Ogata ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Shinichi Shutoh ,  Tatsuo Higuchi ,  Shigeo Takeuchi ,  Taturu Toba ,  Teruo Tanaka

IPC分类号： G06F15/173 ,  G06F15/80 ,  G06F15/163

CPC分类号： G06F15/17368

摘要： In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a receiving-end processor group, a network includes transfer control circuits. A crossbar switch includes transfer control circuits associated with output ports and a boundary register group. When a partial broadcast message is transferred from an input port in the downstream direction of an output port, it is decided whether a belonging to the partial broadcast range associated with a connected to the particular input port is connected to the particular output port, whereby the particular partial broadcast message is transferred from the same output port.

摘要翻译： 为了确定消息到接收端处理器组的传送路径，处理器包括路由位生成电路，并且交换交换机包括部分广播路径控制电路和路径控制信息改变电路。 为了定义接收端处理器组的范围，网络包括传送控制电路。 交叉开关包括与输出端口和边界寄存器组相关联的传输控制电路。 当在输出端口的下游方向上从输入端口传送部分广播消息时，确定属于与连接到特定输入端口的连接的部分广播范围是否连接到特定输出端口，由此 特定的部分广播消息从相同的输出端口传送。

公开(公告)号：US5710935A

公开(公告)日：1998-01-20

申请号：US466462

申请日：1995-06-06

申请人： Thomas Norman Barker ,  Clive Allan Collins ,  Michael Charles Dapp ,  James Warren Dieffenderfer ,  Donald George Grice ,  Peter Michael Kogge ,  David Christopher Kuchinski ,  Billy Jack Knowles ,  Donald Michael Lesmeister ,  Richard Ernest Miles ,  Richard Edward Nier ,  Eric Eugene Retter ,  Robert Reist Richardson ,  David Bruce Rolfe ,  Nicholas Jerome Schoonover ,  Vincent John Smoral ,  James Robert Stupp ,  Paul Amba Wilkinson

发明人： Thomas Norman Barker ,  Clive Allan Collins ,  Michael Charles Dapp ,  James Warren Dieffenderfer ,  Donald George Grice ,  Peter Michael Kogge ,  David Christopher Kuchinski ,  Billy Jack Knowles ,  Donald Michael Lesmeister ,  Richard Ernest Miles ,  Richard Edward Nier ,  Eric Eugene Retter ,  Robert Reist Richardson ,  David Bruce Rolfe ,  Nicholas Jerome Schoonover ,  Vincent John Smoral ,  James Robert Stupp ,  Paul Amba Wilkinson

IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F7/483 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F15/8092 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889 ,  G06F9/3891 ,  F02B2075/027

摘要： A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

摘要翻译： 一种具有多个处理器和存储器的计算机系统，所述存储器包括具有多个相似处理器存储器元件的多个可伸缩节点。 每个处理器存储器元件具有用于在节点内与节点内的其它类似处理器存储器元件通信的多个通信路径。 每个处理器存储器元件还具有用于将节点外部通信到另一个类似计算机系统的可伸缩节点的通信路径。

公开(公告)号：US5685010A

公开(公告)日：1997-11-04

申请号：US603839

申请日：1996-02-22

申请人： Shigeki Yoda

发明人： Shigeki Yoda

IPC分类号： G06F13/12 ,  G06F13/00 ,  G06F13/18 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177

CPC分类号： G06F15/17368 ,  G06F13/18

摘要： A data transfer control device comprising an instruction decoding unit for receiving an transfer instruction from an arithmetic processing unit provided in the cluster and decoding the content thereof, some instruction storage units for storing the transfer instruction, a shared memory access unit for reading and writing the data through access to the shared memory provided in the cluster, a data transfer unit for delivering the data read out by the shared memory access unit to the network among clusters, as well as delivering the received data through the network among clusters to the shared memory access unit, and a transfer control unit for controlling the shared memory access control unit and the data transfer unit according to the transfer instruction which is read out from the instruction storage unit, wherein the instruction decoding unit classifies the transfer instruction into an urgent transfer instruction or a non-urgent transfer instruction on the basis of the decoded result thereof, so to store it into one of the instruction storage unit separately, and the transfer control unit reads out the transfer instruction preferentially from the instruction storage unit which stores the urgent transfer instruction.

摘要翻译： 一种数据传输控制装置，包括：指令解码单元，用于从设置在所述集群中的算术处理单元接收转移指令并对其内容进行解码;存储转移指令的一些指令存储单元;用于读取和写入的共享存储器存取单元 通过访问在集群中提供的共享存储器的数据，数据传送单元，用于将由共享存储器访问单元读出的数据传送到集群之间的网络，以及通过集群中的网络将接收到的数据传送到共享存储器 访问单元和用于根据从指令存储单元读出的传送指令来控制共享存储器访问控制单元和数据传送单元的传送控制单元，其中指令解码单元将传送指令分类为紧急传送指令 或基于解码后的非紧急转移指令 将其分别存储到指令存储单元之一中，并且传送控制单元优先从存储紧急传送指令的指令存储单元读出传送指令。

公开(公告)号：US5617538A

公开(公告)日：1997-04-01

申请号：US249653

申请日：1994-05-26

申请人： Steven K. Heller

发明人： Steven K. Heller

IPC分类号： G06F15/173 ,  G06F13/00

CPC分类号： G06F15/17368

摘要： A computer system comprises a plurality of processing elements interconnected by a communications network. The communications network has a series of network addresses each identifying a location in the network, each processing element has an associated network address in the series. The communications network transfers messages transmitted by the processing elements in accordance with a respective address portion associated with each message, thereby to transfer the messages among the processing elements. Each processing element includes a message generator and a message transmitter. The message generator generates, during a message transfer operation, a series of messages for transmission over the communications network to others of the processing elements in the system, each message having an address portion whose contents enable the communications network to transfer the message from the processing element generating the message to a processing element to receive the message. The message generator generates the messages such that address portions of the successive messages in the series are transferred to processing elements having successive network addresses. The message transmitter iteratively transmits the series of messages generated by the message generator, the message transmitters of the processing elements which have successive network addresses selecting, as initial messages to be transmitted, messages having address portions to be transmitted to processing elements which have succeeding network addresses, thereby to effect a skewing of the messages transferred over the communications network.

摘要翻译： 计算机系统包括由通信网络互连的多个处理元件。 通信网络具有一系列网络地址，每个网络地址标识网络中的位置，每个处理元件具有该系列中的相关网络地址。 通信网络根据与每个消息相关联的相应地址部分传送由处理元件发送的消息，从而在处理元件之间传送消息。 每个处理元件包括消息发生器和消息发送器。 消息发生器在消息传送操作期间产生一系列用于通过通信网络传输到系统中的处理元件的其他消息的消息，每个消息具有地址部分，其内容使通信网络能够从处理传送消息 将消息生成到处理元件以接收消息。 消息生成器生成消息，使得系列中的连续消息的地址部分被传送到具有连续网络地址的处理元件。 消息发射机迭代地发送由消息发生器产生的一系列消息，具有连续网络地址选择的处理元件的消息发送器作为要发送的初始消息，具有要发送到具有成功网络的处理元件的地址部分的消息 从而实现通过通信网络传送的消息的偏斜。

公开(公告)号：US5615360A

公开(公告)日：1997-03-25

申请号：US310005

申请日：1994-09-21

申请人： John D. Bezek ,  Peter M. Kogge

发明人： John D. Bezek ,  Peter M. Kogge

IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06F17/30 ,  G06F12/00

CPC分类号： G06F15/17368 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F7/483 ,  F02B2075/027 ,  Y10S707/99936

摘要： The computer system has its parallel and serial implementations, its serial and parallel network and multi-processor configurations, with tight and loose coupling among processors. The computer system has a CAM coupled to the computer system or imbedded therein. CAM requests may be processed serially, or as parallel queries and coupled with PAPS (Parallel Associative Processor System) capabilities (P-CAM). The computer system may be configured as an expert system preferably having combined tuple space (TS) and CAM (content addressable memory) resources, an inference engine and a knowledge base. As an expert system, improvements for production processing are provided which surpass prior ad performance represented by RETE and CLIPS. An inferencing process for production systems is disclosed, and a process for working memory element assertions. The computer system is provided with a language construct which is language independent in the form of a sub-set paradigm having three basic operators and three basic extensions. The basic primitive sub-set paradigm including OUT(); IN() and READ(). Extensions of said basic sub-set are Sample(); SampleList(); and ReadList(). These primitives may be used with LINDA, and with various compilers. EVAL of LINDA is not used but instead the sub-set paradigm is used with CAM for tuple space operations in data base applications. The language construct paradigm is use to envelope and control CAM operations.

摘要翻译： 计算机系统具有并行和串行实现，其串行和并行网络和多处理器配置，处理器之间具有紧密和松散的耦合。 计算机系统具有耦合到计算机系统或嵌入其中的CAM。 CAM请求可以串行处理，也可以作为并行查询，并与PAPS（并行关联处理器系统）功能（P-CAM）相结合。 计算机系统可以被配置为优选地具有组合元组空间（TS）和CAM（内容可寻址存储器）资源，推理机和知识库的专家系统。 作为一个专家系统，提供了生产处理方面的改进，超越了RETE和CLIPS所代表的先前的广告效果。 公开了生产系统的推理过程，以及用于处理存储器元件断言的过程。 计算机系统具有语言独立的语言结构，其具有具有三个基本操作符和三个基本扩展的子集范例的形式。 包括OUT（）的基本原语子集范例; IN（）和READ（）。 所述基本子集的扩展是Sample（）; SampleList（）; 和ReadList（）。 这些原语可以与LINDA和各种编译器一起使用。 不使用LINDA的EVAL，而是使用子集范例与CAM一起用于数据库应用程序中的元组空间操作。 语言构建范例用于包络和控制CAM操作。

公开(公告)号：US5615309A

公开(公告)日：1997-03-25

申请号：US356925

申请日：1994-12-14

申请人： John D. Bezek ,  Peter M. Kogge

发明人： John D. Bezek ,  Peter M. Kogge

IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06N5/04 ,  G06F15/18

CPC分类号： G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F7/483 ,  G06N5/046 ,  F02B2075/027 ,  Y10S707/99933

摘要： A computer system, and its parallel and serial implementations, its serial and parallel network and multi-processor configurations, with tight and loose coupling among processors. The computer system has a CAM coupled to the computer system or imbedded therein. CAM requests may be processed serially, or as parallel queries and coupled with PAPS (Parallel Associative Processor System) capabilities (P-CAM). The computer system may be configured as an expert system preferably having combined tuple space (TS) and CAM (content addressable memory) resources, an inference engine and a knowledge base. As an expert system, improvements for production processing are provided which surpass prior art performance represented by RETE and CLIPS. An inferencing process for production systems is disclosed, and a process for working memory element assertions. The computer system is provided with a language construct which is language independent in the form of a sub-set paradigm having three basic operators and three basic extensions. The basic primitive sub-set paradigm including OUT(); IN() and READ(). Extensions of said basic sub-set are Sample(); SampleList(); and ReadList(). These primitives may be used with LINDA, and with various compilers. EVAL of LINDA is not used but instead the sub-set paradigm is used with CAM for tuple space operations in data base applications. The language construct paradigm is use to envelope and control CAM operations.

摘要翻译： 计算机系统及其并行和串行实现，其串行和并行网络和多处理器配置，处理器之间的紧耦合和松散耦合。 计算机系统具有耦合到计算机系统或嵌入其中的CAM。 CAM请求可以串行处理，也可以作为并行查询，并与PAPS（并行关联处理器系统）功能（P-CAM）相结合。 计算机系统可以被配置为优选地具有组合元组空间（TS）和CAM（内容可寻址存储器）资源，推理机和知识库的专家系统。 作为专家系统，提供了超越RETE和CLIPS代表的现有技术性能的生产处理方面的改进。 公开了生产系统的推理过程，以及用于处理存储器元件断言的过程。 计算机系统具有语言独立的语言结构，其具有具有三个基本操作符和三个基本扩展的子集范例的形式。 包括OUT（）的基本原语子集范例; IN（）和READ（）。 所述基本子集的扩展是Sample（）; SampleList（）; 和ReadList（）。 这些原语可以与LINDA和各种编译器一起使用。 不使用LINDA的EVAL，而是使用子集范例与CAM一起用于数据库应用程序中的元组空间操作。 语言构建范例用于包络和控制CAM操作。

公开(公告)号：US5590345A

公开(公告)日：1996-12-31

申请号：US887630

申请日：1992-05-22

申请人： Thomas N. Barker ,  Clive A. Collins ,  Michael C. Dapp ,  James W. Dieffenderfer ,  Donald G. Grice ,  Peter M. Kogge ,  David C. Kuchinski ,  Billy J. Knowles ,  Donald M. Lesmeister ,  Richard E. Miles ,  Richard E. Nier ,  Eric E. Retter ,  Robert R. Richardson ,  David B. Rolfe ,  Nicholas J. Schoonover ,  Vincent J. Smoral ,  James R. Stupp ,  Paul A. Wilkinson

发明人： Thomas N. Barker ,  Clive A. Collins ,  Michael C. Dapp ,  James W. Dieffenderfer ,  Donald G. Grice ,  Peter M. Kogge ,  David C. Kuchinski ,  Billy J. Knowles ,  Donald M. Lesmeister ,  Richard E. Miles ,  Richard E. Nier ,  Eric E. Retter ,  Robert R. Richardson ,  David B. Rolfe ,  Nicholas J. Schoonover ,  Vincent J. Smoral ,  James R. Stupp ,  Paul A. Wilkinson

IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F7/483 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F15/8092 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889 ,  G06F9/3891 ,  F02B2075/027

摘要： A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

摘要翻译： 一种具有多个处理器和存储器的计算机系统，所述存储器包括具有多个相似处理器存储器元件的多个可伸缩节点。 每个处理器存储器元件具有用于在节点内与节点内的其它类似处理器存储器元件通信的多个通信路径。 每个处理器存储器元件还具有用于将节点外部通信到另一个类似计算机系统的可伸缩节点的通信路径。

公开(公告)号：US5361334A

公开(公告)日：1994-11-01

申请号：US31930

申请日：1993-03-15

申请人： Robin A. Cawley

发明人： Robin A. Cawley

IPC分类号： G06F15/16 ,  G06F9/44 ,  G06F9/46 ,  G06F9/52 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F15/20

CPC分类号： G06F9/52 ,  G06F15/17368 ,  G06F9/4436 ,  G06F9/462

摘要： A data processing system having a plurality of processing units (C1, C2), a plurality of memory units (M1, M2) and a communication system providing communication between the processing units and the memory units. The processing units each have a plurality of register sets (R1, R2) allowing them to run a plurality of processes. When a process requires data from memory, which it receives over the communication system, its respective processing unit processes another of its processes until that requires data. Data is transmitted over the communication system, which may be configured as a grid, in the form of packets. The grid is configured from routing devices which include first-in-first-out devices for the buffering of packets. The system facilitates the construction of circuits integrated onto a singel wafter of semiconducting material. Furthermore the grid structure may also be employed as a local area network and computers having a similar architecture may be connected to the network providing a processing facility of considerable power.

摘要翻译： 一种具有多个处理单元（C1，C2），多个存储单元（M1，M2）和提供处理单元与存储单元之间的通信的通信系统的数据处理系统。 处理单元各自具有允许它们运行多个处理的多个寄存器组（R1，R2）。 当进程需要通过通信系统接收的来自存储器的数据时，其各自的处理单元处理另一个进程，直到需要数据。 通过通信系统传输数据，通信系统可以以数据包的形式配置为网格。 网格由包括用于缓冲分组的先进先出设备的路由设备配置。 该系统有助于整合到半导体材料的单一晶体上的电路的构建。 此外，网格结构也可以用作局域网，并且具有类似架构的计算机可以连接到提供相当大功率的处理设备的网络。