公开(公告)号：US5710935A

公开(公告)日：1998-01-20

申请号：US466462

申请日：1995-06-06

申请人： Thomas Norman Barker ,  Clive Allan Collins ,  Michael Charles Dapp ,  James Warren Dieffenderfer ,  Donald George Grice ,  Peter Michael Kogge ,  David Christopher Kuchinski ,  Billy Jack Knowles ,  Donald Michael Lesmeister ,  Richard Ernest Miles ,  Richard Edward Nier ,  Eric Eugene Retter ,  Robert Reist Richardson ,  David Bruce Rolfe ,  Nicholas Jerome Schoonover ,  Vincent John Smoral ,  James Robert Stupp ,  Paul Amba Wilkinson

发明人： Thomas Norman Barker ,  Clive Allan Collins ,  Michael Charles Dapp ,  James Warren Dieffenderfer ,  Donald George Grice ,  Peter Michael Kogge ,  David Christopher Kuchinski ,  Billy Jack Knowles ,  Donald Michael Lesmeister ,  Richard Ernest Miles ,  Richard Edward Nier ,  Eric Eugene Retter ,  Robert Reist Richardson ,  David Bruce Rolfe ,  Nicholas Jerome Schoonover ,  Vincent John Smoral ,  James Robert Stupp ,  Paul Amba Wilkinson

IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F7/483 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F15/8092 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889 ,  G06F9/3891 ,  F02B2075/027

摘要： A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

摘要翻译： 一种具有多个处理器和存储器的计算机系统，所述存储器包括具有多个相似处理器存储器元件的多个可伸缩节点。 每个处理器存储器元件具有用于在节点内与节点内的其它类似处理器存储器元件通信的多个通信路径。 每个处理器存储器元件还具有用于将节点外部通信到另一个类似计算机系统的可伸缩节点的通信路径。

公开(公告)号：US5963746A

公开(公告)日：1999-10-05

申请号：US468500

申请日：1995-06-06

申请人： Thomas Norman Barker ,  Clive Allan Collins ,  Michael Charles Dapp ,  James Warren Dieffenderfer ,  Billy Jack Knowles ,  Donald Michael Lesmeister ,  Richard Ernest Miles ,  Richard Edward Nier ,  Robert Reist Richardson ,  David Bruce Rolfe ,  Vincent John Smoral

发明人： Thomas Norman Barker ,  Clive Allan Collins ,  Michael Charles Dapp ,  James Warren Dieffenderfer ,  Billy Jack Knowles ,  Donald Michael Lesmeister ,  Richard Ernest Miles ,  Richard Edward Nier ,  Robert Reist Richardson ,  David Bruce Rolfe ,  Vincent John Smoral

IPC分类号： G06F9/38 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F15/8007

摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

公开(公告)号：US5842031A

公开(公告)日：1998-11-24

申请号：US468045

申请日：1995-06-06

申请人： Thomas Norman Barker ,  Clive Allan Collins ,  Michael Charles Dapp ,  James Warren Dieffenderfer ,  Donald George Grice ,  Peter Michael Kogge ,  David Christoper Kuchinski ,  Billy Jack Knowles ,  Donald Michael Lesmeister ,  Richard Ernest Miles ,  Richard Edward Nier ,  Eric Eugene Retter ,  Robert Reist Richardson ,  David Bruce Rolfe ,  Nicholas Jerome Schoonover ,  Vincent John Smoral ,  James Robert Stupp ,  Paul Amba Wilkinson

发明人： Thomas Norman Barker ,  Clive Allan Collins ,  Michael Charles Dapp ,  James Warren Dieffenderfer ,  Donald George Grice ,  Peter Michael Kogge ,  David Christoper Kuchinski ,  Billy Jack Knowles ,  Donald Michael Lesmeister ,  Richard Ernest Miles ,  Richard Edward Nier ,  Eric Eugene Retter ,  Robert Reist Richardson ,  David Bruce Rolfe ,  Nicholas Jerome Schoonover ,  Vincent John Smoral ,  James Robert Stupp ,  Paul Amba Wilkinson

IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F7/483 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F15/8092 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889 ,  G06F9/3891 ,  F02B2075/027

摘要： A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

公开(公告)号：US5717943A

公开(公告)日：1998-02-10

申请号：US465926

申请日：1995-06-05

申请人： Thomas Norman Barker ,  Clive Allan Collins ,  Michael Charles Dapp ,  James Warren Dieffenderfer ,  Donald George Grice ,  Peter Michael Kogge ,  David Christopher Kuchinski ,  Billy Jack Knowles ,  Donald Michael Lesmeister ,  Richard Ernest Miles ,  Richard Edward Nier ,  Eric Eugene Retter ,  Robert Reist Richardson ,  David Bruce Rolfe ,  Nicholas Jerome Schoonover ,  Vincent John Smoral ,  James Robert Stupp ,  Paul Amba Wilkinson

发明人： Thomas Norman Barker ,  Clive Allan Collins ,  Michael Charles Dapp ,  James Warren Dieffenderfer ,  Donald George Grice ,  Peter Michael Kogge ,  David Christopher Kuchinski ,  Billy Jack Knowles ,  Donald Michael Lesmeister ,  Richard Ernest Miles ,  Richard Edward Nier ,  Eric Eugene Retter ,  Robert Reist Richardson ,  David Bruce Rolfe ,  Nicholas Jerome Schoonover ,  Vincent John Smoral ,  James Robert Stupp ,  Paul Amba Wilkinson

IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F7/483 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F15/8092 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889 ,  G06F9/3891 ,  F02B2075/027

摘要： A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

公开(公告)号：US5794059A

公开(公告)日：1998-08-11

申请号：US282101

申请日：1994-07-28

申请人： Thomas Norman Barker ,  Clive Allan Collins ,  Michael Charles Dapp ,  James Warren Dieffenderfer ,  Billy Jack Knowles ,  David Bruce Rolfe

发明人： Thomas Norman Barker ,  Clive Allan Collins ,  Michael Charles Dapp ,  James Warren Dieffenderfer ,  Billy Jack Knowles ,  David Bruce Rolfe

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06F15/16

CPC分类号： G06F9/3802 ,  G06F15/17343 ,  G06F15/17381 ,  G06F15/803 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAWM processing while incorporating processing elements on a single chip, with nodes connected in an n-dimensional modified non-binary hypercube. In a 4-dimensional modified non-binary hypercube embodiment, each node includes either processor memory elements on a single chip, each processor memory element having its own associated processing element, significant memory, and I/O, with each processor memory element supporting an external port. Pairs of ports are associated with each dimension, labeled X, Y, W, and Z. Eight nodes are connected in the X dimension to form a ring. Corresponding nodes from eight such rings are connected into rings in the Y dimension to form an 8.times.8 array of nodes, referred to as a cluster. Corresponding nodes of eight clusters are connected into ring (64 rings) in the Z dimension, forming an 8.times.8.times.8 array of nodes referred to as a "cluster ring". Corresponding nodes of eight cluster rings are connected into rings in the W dimension.

摘要翻译： 用于大规模并行应用的并行阵列处理器由具有DRAWM处理的低功率CMOS形成，同时在单个芯片上并入处理元件，节点连接在n维修改的非二进制超立方体中。 在4维修改的非二进制超立方体实施例中，每个节点包括单个芯片上的处理器存储器元件，每个处理器存储器元件具有其自己的相关处理元件，有效存储器和I / O，每个处理器存储器元件支持 外部端口 一对端口与每个尺寸相关联，标记为X，Y，W和Z.八个节点连接在X维中以形成环。 来自八个这样的环的相应节点连接到Y维中的环中以形成称为簇的8×8节点阵列。 八个簇的相应节点在Z维中连接成环（64个环），形成称为“簇环”的节点的8×8×8阵列。 八个群集环的相应节点连接到W维中的环中。

公开(公告)号：US5963745A

公开(公告)日：1999-10-05

申请号：US430114

申请日：1995-04-27

申请人： Clive Allan Collins ,  Michael Charles Dapp ,  James Warren Dieffenderfer ,  David Christopher Kuchinski ,  Billy Jack Knowles ,  Richard Edward Nier ,  Eric Eugene Retter ,  Robert Reist Richardson ,  David Bruce Rolfe ,  Vincent John Smoral

发明人： Clive Allan Collins ,  Michael Charles Dapp ,  James Warren Dieffenderfer ,  David Christopher Kuchinski ,  Billy Jack Knowles ,  Richard Edward Nier ,  Eric Eugene Retter ,  Robert Reist Richardson ,  David Bruce Rolfe ,  Vincent John Smoral

IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06F15/16

CPC分类号： G06F9/3887 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F7/483 ,  G06F9/30 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/38 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  F02B2075/027

摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processor memory elements on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. The architecture uses all the pins for networking. Each chip has eight 16 bit processors, and eight respective 32K memories. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. The scalable chip has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. A fully distributed programmable router is provided by the processing memory elements that form a node. There is program compatibility for the fully scalable system.

摘要翻译： 用于大规模并行应用的并行阵列处理器由具有DRAM处理的低功率CMOS形成，同时在单个芯片上并入处理元件。 单个芯片上的八个处理器存储器元件具有它们自己的相关联的处理元件，显着的存储器和I / O，并且与基于超立方体但是被修改的拓扑互连。 然后，这些节点由环形网络拓扑中的超立方体，修改的超立方体，环或环组成。 该架构使用所有引脚进行网络连接。 每个芯片有八个16位处理器，八个相应的32K存储器。 I / O具有芯片上的多个处理器共享的三个内部端口和一个外部端口。 提供了重要的软件灵活性，以便能够快速实现以常用语言编写的现有程序。 可扩展芯片具有用于广播和异步SIMD，MIMD和SIMIMD（SIMD / MIMD）的内部和外部连接，具有模式的动态切换。 完全分布式可编程路由器由形成节点的处理存储器元件提供。 完全可扩展的系统具有程序兼容性。