公开(公告)号：US20230413695A1

公开(公告)日：2023-12-21

申请号：US18239108

申请日：2023-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/826 ,  H10N70/231 ,  H10N70/011 ,  H10B63/00

Abstract: A manufacturing method of a memory device includes following steps. A memory unit including a first electrode, a second electrode, and a memory material layer is formed on a substrate. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A first spacer layer including a first portion, a second portion, and a third portion is formed on a sidewall of the memory unit. The first portion is disposed on a sidewall of the first electrode. The second portion is disposed on a sidewall of the second electrode. The third portion is disposed above the memory unit in the vertical direction and connected with the second portion. A thickness of the second portion in a horizontal direction is greater than that of the first portion in the horizontal direction.

公开(公告)号：US11812667B2

公开(公告)日：2023-11-07

申请号：US17341316

申请日：2021-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection. A material composition of the second metal interconnection is different from a material composition of the first metal interconnection.

公开(公告)号：US11785785B2

公开(公告)日：2023-10-10

申请号：US17336295

申请日：2021-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Tai-Cheng Hou ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.

公开(公告)号：US20220406996A1

公开(公告)日：2022-12-22

申请号：US17377367

申请日：2021-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A manufacturing method of a memory device includes the following steps. Memory units are formed on a substrate. Each of the memory units includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a sidewall portion of the non-conformal spacer layer and a sidewall portion of the conformal spacer layer in the vertical direction.

公开(公告)号：US20220102629A1

公开(公告)日：2022-03-31

申请号：US17084639

申请日：2020-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo

IPC: H01L45/00 ,  H01L27/24

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a resistance random access memory (RRAM), a first spacer located at two sides of the RRAM, a second spacer located outside the first spacer, wherein the second spacer contains metal material or metal oxide material, and a third spacer located outside the second spacer.

公开(公告)号：US20210288107A1

公开(公告)日：2021-09-16

申请号：US17336279

申请日：2021-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Tai-Cheng Hou ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first top electrode on the first MTJ and a second top electrode on the second MTJ, a passivation layer between the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on and directly contacting the passivation layer and around the first MTJ and the second MTJ. Preferably, a top surface of the passivation layer includes a V-shape and a valley point of the V-shape is higher than a bottom surface of the first top electrode.

公开(公告)号：US11056536B2

公开(公告)日：2021-07-06

申请号：US16544923

申请日：2019-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Tai-Cheng Hou ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.

公开(公告)号：US10847709B1

公开(公告)日：2020-11-24

申请号：US16439712

申请日：2019-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Meng-Jun Wang ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A semiconductor device includes: a magnetic tunneling junction (MTJ) on a substrate; a first inter-metal dielectric (IMD) layer around the MTJ; a metal interconnection on and directly contacting the MTJ; a second IMD layer on the first IMD layer and around the metal interconnection; and a metal oxide layer on the second IMD layer and around the metal interconnection.