公开(公告)号：US20230262991A1

公开(公告)日：2023-08-17

申请号：US17672355

申请日：2022-02-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Chen Chang ,  Tzu-Yu Chen ,  Sheng-Hung Shih ,  Kuo-Chi Tu ,  Wen-Ting Chu

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: The present disclosure relates to an integrated chip including a first ferroelectric layer over a substrate. A first electrode layer is over the substrate and on a first side of the first ferroelectric layer. A second electrode layer is over the substrate and on a second side of the first ferroelectric layer, opposite the first side. A first barrier layer is between the first ferroelectric layer and the first electrode layer. A bandgap energy of the first barrier layer is greater than a bandgap energy of the first ferroelectric layer.

公开(公告)号：US20220351769A1

公开(公告)日：2022-11-03

申请号：US17866946

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair

IPC: G11C11/22 ,  H01L27/11592 ,  H01L27/1159 ,  H01L29/51

Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is disposed over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random-access memory (FeRAM) device is disposed over the substrate between the select gate and the first source/drain region. A first sidewall spacer, including one or more dielectric materials, is arranged laterally between the select gate and the FeRAM device. An inter-level dielectric (ILD) structure laterally surrounds the FeRAM device and the select gate and vertically overlies a top surface of the first sidewall spacer.

公开(公告)号：US20220246838A1

公开(公告)日：2022-08-04

申请号：US17724920

申请日：2022-04-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tong-Chern Ong ,  Wen-Ting Chu ,  Yu-Wen Liao ,  Kuei-Hung Shen ,  Kuo-Yuan Tu ,  Sheng-Huang Huang

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/00

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.

公开(公告)号：US11387411B2

公开(公告)日：2022-07-12

申请号：US16994359

申请日：2020-08-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Yang Chang ,  Hsia-Wei Chen ,  Chin-Chieh Yang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L45/00

Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

公开(公告)号：US20220139959A1

公开(公告)日：2022-05-05

申请号：US17574010

申请日：2022-01-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsiang Chang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Tzu-Yu Chen ,  Fu-Chen Chang

IPC: H01L27/11585 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  G11C11/22

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

公开(公告)号：US20220077165A1

公开(公告)日：2022-03-10

申请号：US17528611

申请日：2021-11-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Chih-Hsiang Chang ,  Fu-Chen Chang

IPC: H01L27/11502 ,  H01L27/11507 ,  H01L49/02 ,  G11C11/22 ,  H01L27/11504

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The top electrode has interior surfaces defining a recess within an upper surface of the top electrode. A masking layer contacts a bottom of the recess and extends to over the upper surface of the top electrode. An interconnect extends through the masking layer and to the top electrode. The interconnect is directly over the upper surface of the top electrode.

公开(公告)号：US11239279B2

公开(公告)日：2022-02-01

申请号：US16680203

申请日：2019-11-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Chieh Yang ,  Hsia-Wei Chen ,  Chih-Yang Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  H01L29/66 ,  H01L45/00 ,  H01L21/265 ,  H01L21/266 ,  H01L29/08 ,  H01L29/78

Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.

公开(公告)号：US20200083294A1

公开(公告)日：2020-03-12

申请号：US16680203

申请日：2019-11-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Chieh Yang ,  Hsia-Wei Chen ,  Chih-Yang Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  H01L29/66 ,  H01L45/00 ,  H01L21/265 ,  H01L21/266 ,  H01L29/08 ,  H01L29/78

Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.

公开(公告)号：US10475852B2

公开(公告)日：2019-11-12

申请号：US16160675

申请日：2018-10-15

Applicant: Taiwan Semiconductor Manufacturing Company., Ltd.

Inventor： Chin-Chieh Yang ,  Hsia-Wei Chen ,  Chih-Yang Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  H01L29/66 ,  H01L45/00 ,  H01L21/265 ,  H01L21/266 ,  H01L29/08 ,  H01L29/78

Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain of the FET has a higher doping concentration than the source of the FET. The resistive memory element is coupled with the drain via a portion of an interconnect structure.

公开(公告)号：US10388868B2

公开(公告)日：2019-08-20

申请号：US15161443

申请日：2016-05-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chi Tu ,  Chih-Yang Chang ,  Hsia-Wei Chen ,  Chin-Chieh Yang ,  Sheng-Hung Shih ,  Wen-Chun You ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: G11C11/56 ,  G11C14/00 ,  H01L45/00

Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.