公开(公告)号：US11442482B2

公开(公告)日：2022-09-13

申请号：US17010064

申请日：2020-09-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Chin-I Su

IPC: G05F1/575 ,  H02M3/155 ,  G05F1/46 ,  G05F1/577

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

公开(公告)号：US11437099B2

公开(公告)日：2022-09-06

申请号：US17240534

申请日：2021-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Cheng Chou ,  Tien-Yen Wang

IPC: G11C13/00

Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.

公开(公告)号：US11336174B2

公开(公告)日：2022-05-17

申请号：US16657221

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Cheng Chou ,  Tien-Yen Wang

IPC: H02M3/07 ,  G11C13/00

Abstract: A system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.

公开(公告)号：US11309022B2

公开(公告)日：2022-04-19

申请号：US17135169

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-An Lai ,  Chung-Cheng Chou ,  Yu-Der Chih

IPC: G11C13/00 ,  G11C7/10 ,  G11C7/04

Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.

公开(公告)号：US20210249075A1

公开(公告)日：2021-08-12

申请号：US17240534

申请日：2021-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Cheng Chou ,  Tien-Yen Wang

IPC: G11C13/00

Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.

公开(公告)号：US20210119531A1

公开(公告)日：2021-04-22

申请号：US16657221

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Cheng Chou ,  Tien-Yen Wang

IPC: H02M3/07 ,  G11C13/00

Abstract: A system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.

公开(公告)号：US10755780B2

公开(公告)日：2020-08-25

申请号：US16273608

申请日：2019-02-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Pei-Ling Tseng

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/08 ,  G11C7/12 ,  G11C7/06

Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.

公开(公告)号：US20200243135A1

公开(公告)日：2020-07-30

申请号：US16694114

申请日：2019-11-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Cheng Chou ,  Tien-Yen Wang

IPC: G11C13/00

Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.

公开(公告)号：US09985203B2

公开(公告)日：2018-05-29

申请号：US14081916

申请日：2013-11-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jonathan Tehan Chen ,  Chung-Cheng Chou ,  Po-Hao Lee ,  Kuo-Chi Tu

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: The present disclosure provides resistive random access memory (RRAM) structures and methods of making the same. The RRAM structures include a bottom electrode having protruded step portion that allows formation of a self-aligned conductive path with a top electrode during operation. The protruded step portion may have an inclination angle of about 30 degrees to 150 degrees. Multiple RRAM structures may be formed by etching through a RRAM stack.

公开(公告)号：US09977441B2

公开(公告)日：2018-05-22

申请号：US15093211

申请日：2016-04-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Cheng Chou ,  Po-Hao Lee

IPC: G05F1/46 ,  G05F1/575 ,  H02M1/12 ,  H02M3/338

CPC classification number: G05F1/468 ,  G05F1/46 ,  G05F1/575 ,  H02M1/12 ,  H02M3/3382

Abstract: A device is configured to provide low dropout regulation. An amplifier stage includes a first transistor electrically connected to an output of the device, and a second transistor. A current mirror includes a third transistor electrically connected to the second transistor, and a fourth transistor electrically connected to the third transistor. The auxiliary current source has a control terminal electrically connected to a gate electrode of the fourth transistor. The pull down stage includes a fifth transistor having a gate electrode electrically connected to a drain electrode of the first transistor, and a sixth transistor having a gate electrode electrically connected to the gate electrode of the fourth transistor. The pull up transistor has a gate electrode electrically connected to a drain electrode of the fifth transistor. The first capacitor has a first terminal electrically connected to the gate electrode of the first transistor.