公开(公告)号：US10037891B2

公开(公告)日：2018-07-31

申请号：US15427561

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Atsushi Harikai

IPC: H01L21/00 ,  H01L21/3065 ,  H01L21/78 ,  H01L23/544 ,  H01L21/311 ,  H01L21/67 ,  H01L21/683 ,  H01L21/687

CPC classification number: H01L21/3065 ,  H01L21/30655 ,  H01L21/31138 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/6831 ,  H01L21/68742 ,  H01L21/68785 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/5446

Abstract: A manufacturing method of an element chip includes a preparation process of adhering a holding sheet to the first main surface of a substrate so as to prepare the substrate held by the holding sheet, a plasma dicing process of performing plasma etching on the isolation region of the substrate to the first main surface so as to divide the substrate into the plurality of element chips. The plasma dicing process includes a first plasma etching process of performing plasma etching on a the isolation region partially in a thickness direction while a cooling gas is supplied between the stage and the holding sheet, and a second plasma etching process of stopping a supply of the cooling gas after the first plasma etching process, and performing plasma etching on a remaining portion of the isolation region.

公开(公告)号：US09953906B2

公开(公告)日：2018-04-24

申请号：US15408750

申请日：2017-01-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Noriyuki Matsubara

IPC: H01L21/784 ,  H01L23/498 ,  H01L21/3065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/563 ,  H01L21/78 ,  H01L21/784 ,  H01L23/3171 ,  H01L23/3185 ,  H01L24/09 ,  H01L24/89 ,  H01L2224/80801 ,  H01L2224/81 ,  H01L2924/15323

Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by insulating film, the substrate is divided into element chips by exposing the substrate to a first plasma, element chips having first surface, second surface, and side surface are held spaced from each other on carrier, insulating film is in a state of being exposed, recessed portions are formed by retreating insulating film by exposing element chips to second plasma for ashing, and then recessed portions are covered by protection films by third plasma for formation of the protection film, thereby suppressing creep-up of the conductive material to side surface in the mounting step.

公开(公告)号：US09941167B2

公开(公告)日：2018-04-10

申请号：US15426199

申请日：2017-02-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Bunzi Mizuno ,  Shogo Okita ,  Mitsuru Hiroshima ,  Tutomu Sakurai ,  Noriyuki Matsubara

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/67 ,  H01L21/683 ,  H01L21/268 ,  H01L21/3065

CPC classification number: H01L21/78 ,  H01J2237/334 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/6831

Abstract: The method includes a laser scribing step of forming an opening including an exposing portion, where the first layer is exposed, by irradiating the dividing region of the substrate with laser light from the first main surface side, forming a remaining region on which the second layer in the dividing region remains around the opening other than the exposing portion, and forming a first damaged region of a surface layer portion of the first layer including the exposing portion and a second damaged region of a surface layer portion of the first layer to be covered by the remaining region on the first layer of the dividing region.

公开(公告)号：US09922899B2

公开(公告)日：2018-03-20

申请号：US15408718

申请日：2017-01-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Noriyuki Matsubara ,  Mitsuru Hiroshima ,  Mitsuhiro Okune

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/544 ,  H01L21/3065 ,  H01L21/02 ,  H01L23/29

CPC classification number: H01L23/3178 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31138 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/293 ,  H01L23/3185 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/5446

Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into the element chips by exposing the substrate to first plasma. Therefore, the element chips having a first surface, a second surface, and a side surface on which a plurality of convex portions are formed are held spaced from each other on a carrier. A protection film is formed on the side surface of the element chip by exposing the element chip to second plasma, at least convex portions formed on the side surface are covered by the protection film in the protection film formation, and creep-up of a conductive material to the side surface is suppressed in the mounting step.

公开(公告)号：US09859144B2

公开(公告)日：2018-01-02

申请号：US15258717

申请日：2016-09-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Noriyuki Matsubara

IPC: H01L21/00 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: In a plasma processing process used for a method of manufacturing element chips by which a plurality of element chips are manufactured by dividing a substrate having a plurality of element regions, the substrate is exposed to first plasma, and thereby the substrate is divided into element chips, and the element chips having first surfaces, second surfaces, and side surfaces connecting the first surfaces to the second surfaces are held with an interval between the element chips on the carrier. The element chips are exposed to second plasma which uses a mixed gas of fluorocarbon and helium as a raw material gas, and thereby a protection film covering the side surfaces is formed, and a conductive material is prevented from creeping up to the side surfaces during a mounting process.

公开(公告)号：US09786472B2

公开(公告)日：2017-10-10

申请号：US14873255

申请日：2015-10-02

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Tetsuhiro Iwai ,  Shogo Okita ,  Syouzou Watanabe

IPC: H01J37/32 ,  C23C16/458 ,  C23C16/50 ,  H01L21/67 ,  H01L21/683 ,  H01L21/687 ,  C23C16/46

CPC classification number: H01J37/3244 ,  C23C16/4586 ,  C23C16/466 ,  C23C16/50 ,  H01J37/321 ,  H01J37/32724 ,  H01L21/67109 ,  H01L21/67132 ,  H01L21/6831 ,  H01L21/68735 ,  H01L21/68742 ,  H01L21/68785

Abstract: A plasma processing apparatus performs plasma processing on a substrate held by a carrier. The carrier includes a frame disposed around the substrate and a holding sheet which holds the substrate and the frame. The plasma processing apparatus includes: a chamber; a stage which is disposed within the chamber and has an upper surface on which the carrier is mounted; a gas hole which is provided at a position of the upper surface opposing a bottom surface of the frame and through which cooling gas is supplied between the stage and the carrier; and a plasma exciting unit which generates plasma within the chamber.

公开(公告)号：US09780021B2

公开(公告)日：2017-10-03

申请号：US15408770

申请日：2017-01-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Noriyuki Matsubara

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3171 ,  H01L24/09 ,  H01L24/89 ,  H01L2224/80801 ,  H01L2924/15323

Abstract: To provide a method of manufacturing an element chip in which creep-up of a conductive material can be suppressed in a mounting step. In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by an insulating film, the substrate is divided into the element chips by exposing the substrate to a first plasma, the element chips having a first surface, a second surface, and a side surface are held spaced from each other on a carrier, and the side surface and the insulating film are in a state of being exposed.