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公开(公告)号：US20190332903A1
公开(公告)日：2019-10-31
申请号：US16505012
申请日：2019-07-08
Applicant: Intel Corporation
Inventor： Kevin Nealis , Anbang Yao , Xiaoming Chen , Elmoustapha Ould-Ahmed-Vall , Sara S. Baghsorkhi , Eriko Nurvitadhi , Balaji Vembu , Nicolas C. Galoppo Von Borries , Rajkishore Barik , Tsung-Han Lin , Kamal Sinha
Abstract: One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a bipolar binary weight associated with a neural network and an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input based on the bipolar binary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.
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Patent Agency Ranking
公开(公告)号：US10410098B2
公开(公告)日：2019-09-10
申请号：US15494710
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Kevin Nealis , Anbang Yao , Xiaoming Chen , Elmoustapha Ould-Ahmed-Vall , Sara S. Baghsorkhi , Eriko Nurvitadhi , Balaji Vembu , Nicolas C. Galoppo Von Borries , Rajkishore Barik , Tsung-Han Lin , Kamal Sinha
IPC: G06F9/30 , G06K9/66 , G06K9/00 , G06F9/38 , G06F9/46 , G06T1/20 , G06N3/04 , G06N3/063 , G06N3/08
Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including an input value and a quantized weight value associated with a neural network and an arithmetic logic unit including a barrel shifter, an adder, and an accumulator register, wherein to execute the decoded instruction, the barrel shifter is to shift the input value by the quantized weight value to generate a shifted input value and the adder is to add the shifted input value to a value stored in the accumulator register and update the value stored in the accumulator register.
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53.发明申请公开(公告)号：US20190139182A1
公开(公告)日：2019-05-09
申请号：US16197783
申请日：2018-11-21
Applicant: Intel Corporation
Inventor： Eriko Nurvitadhi , Balaji Vembu , Nicolas C. Galoppo Von Borries , Rajkishore Barik , Tsung-Han Lin , Kamal Sinha , Nadathur Rajagopalan Satish , Jeremy Bottleson , Farshad Akhbari , Altug Koker , Narayan Srinivasa , Dukhwan Kim , Sara S. Baghsorkhi , Justin E. Gottschlich , Feng Chen , Elmoustapha Ould-Ahmed-Vall , Kevin Nealis , Xiaoming Chen , Anbang Yao
CPC classification number: G06T1/20 , G06F9/3001 , G06F9/3017 , G06F9/3851 , G06F9/3887 , G06F9/3895 , G06N3/04 , G06N3/0445 , G06N3/0454 , G06N3/063 , G06N3/08 , G06N3/084
Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex machine learning compute operation.
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公开(公告)号：US20180315157A1
公开(公告)日：2018-11-01
申请号：US15581167
申请日：2017-04-28
Applicant: Intel Corporation
Inventor： Elmoustapha Ould-Ahmed-Vall , Sara S. Baghsorkhi , Anbang Yao , Kevin Nealis , Xiaoming Chen , Altug Koker , Abhishek R. Appu , John C. Weast , Mike B. Macpherson , Dukhwan Kim , Linda L. Hurd , Ben . Ashbaugh , Barath Lakshmanan , Liwei Ma , Joydeep Ray , Ping T. Tang , Michael S. Strickland
Abstract: One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.
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公开(公告)号：US20180307981A1
公开(公告)日：2018-10-25
申请号：US15494826
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Gokcen Cilingir , Elmoustapha Ould-Ahmed-Vall , Rajkishore Barik , Kevin Nealis , Xiaoming Chen , Justin E. Gottschlich , Prasoonkumar Surti , Chandrasekaran Sakthivel , Abhishek R. Appu , John C. Weast , Sara S. Baghsorkhi , Barnan Das , Narayan Biswal , Stanley J. Baran , Nilesh Shah , Archie Sharma , Mayuresh M. Varerkar
CPC classification number: G06N3/08 , G06F9/3001 , G06F9/3017 , G06F9/3851 , G06F9/3887 , G06F9/3895 , G06F9/46 , G06N3/04 , G06N3/063 , G06T1/20
Abstract: An apparatus to facilitate neural network (NN) training is disclosed. The apparatus includes training logic to receive one or more network constraints and train the NN by automatically determining a best network layout and parameters based on the network constraints.
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公开(公告)号：US20180307950A1
公开(公告)日：2018-10-25
申请号：US15494710
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Kevin Nealis , Anbang Yao , Xiaoming Chen , Elmoustapha Ould-Ahmed-Vall , Sara S. Baghsorkhi , Eriko Nurvitadhi , Balaji Vembu , Nicolas C. Galoppo Von Borries , Rajkishore Barik , Tsung-Han Lin , Kamal Sinha
CPC classification number: G06K9/66 , G06F9/3001 , G06F9/3851 , G06F9/3887 , G06F9/3893 , G06F2207/4824 , G06K9/00973 , G06N3/0445 , G06N3/0454 , G06N3/063 , G06N3/084 , G06T1/20
Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including an input value and a quantized weight value associated with a neural network and an arithmetic logic unit including a barrel shifter, an adder, and an accumulator register, wherein to execute the decoded instruction, the barrel shifter is to shift the input value by the quantized weight value to generate a shifted input value and the adder is to add the shifted input value to a value stored in the accumulator register and update the value stored in the accumulator register.
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