公开(公告)号：US20210265331A1

公开(公告)日：2021-08-26

申请号：US17318344

申请日：2021-05-12

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Liang Wang ,  Rajesh Katkar

IPC: H01L25/16 ,  H01L33/48 ,  H01L23/00 ,  H01L23/48 ,  H01L33/62 ,  H01L23/538

Abstract: Direct-bonded optoelectronic interconnects for high-density integrated photonics are provided. A combined electrical and optical interconnect enables direct-bonding of fully-processed optoelectronic dies or wafers to wafers with optoelectronic driver circuitry. The photonic devices may be III-V semiconductor devices. Direct-bonding to silicon or silicon-on-insulator (SOI) wafers enables the integration of photonics with high-density CMOS and other microelectronics packages. Each bonding surface has an optical window to be coupled by direct-bonding. Coplanar electrical contacts lie to the outside, or may circumscribe the respective optical windows and are also direct-bonded across the interface using metal-to-metal direct-bonding, without interfering with the optical windows. Direct hybrid bonding can accomplish both optical and electrical bonding in one overall operation, to mass-produce mLED video displays. The adhesive-free dielectric-to-dielectric direct bonding and solder-free metal-to-metal direct bonding creates high-density electrical interconnects on the same bonding interface as the bonded optical interconnect. Known-good-dies may be used, which is not possible conventionally, and photolithography over their top surfaces can scale to high density.

公开(公告)号：US11031285B2

公开(公告)日：2021-06-08

申请号：US16143850

申请日：2018-09-27

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/68 ,  H01L25/065 ,  H01L23/532 ,  H01L25/00

Abstract: Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

公开(公告)号：US20200328165A1

公开(公告)日：2020-10-15

申请号：US16846177

申请日：2020-04-10

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Javier A. DeLaCruz ,  Rajesh Katkar

IPC: H01L23/00

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry. The bonded element can include an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation.

公开(公告)号：US10790262B2

公开(公告)日：2020-09-29

申请号：US16363894

申请日：2019-03-25

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Cyprian Emeka Uzoh ,  Jeremy Alfred Theil ,  Liang Wang ,  Rajesh Katkar ,  Guilian Gao ,  Laura Wills Mirkarimi

IPC: H01L21/00 ,  H01L23/00

Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

公开(公告)号：US10658313B2

公开(公告)日：2020-05-19

申请号：US16189804

申请日：2018-11-13

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Javier A. Delacruz ,  Rajesh Katkar ,  Shaowu Huang ,  Gaius Gillman Fountain, Jr. ,  Liang Wang ,  Laura Wills Mirkarimi

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

Abstract: Representative implementations of techniques and devices are used to remedy or mitigate the effects of damaged interconnect pads of bonded substrates. A recess of predetermined size and shape is formed in the surface of a second substrate of the bonded substrates, at a location that is aligned with the damaged interconnect pad on the first substrate. The recess encloses the damage or surface variance of the pad, when the first and second substrates are bonded.

公开(公告)号：US20190198407A1

公开(公告)日：2019-06-27

申请号：US16212471

申请日：2018-12-06

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Shaowu Huang ,  Javier A. DeLaCruz ,  Liang Wang ,  Rajesh Katkar ,  Belgacem Haba

IPC: H01L23/10 ,  H01L23/66

CPC classification number: H01L23/10 ,  H01L23/66 ,  H01L2224/48091 ,  H01L2924/1616 ,  H01L2924/181

Abstract: An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure.

公开(公告)号：US10002844B1

公开(公告)日：2018-06-19

申请号：US15387385

申请日：2016-12-21

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Liang Wang ,  Rajesh Katkar ,  Javier A. DeLaCruz ,  Arkalgud R. Sitaram

IPC: H01L23/10 ,  H01L23/522 ,  H01L23/00 ,  H01L23/498 ,  H01L23/528 ,  H01L23/532

Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.