公开(公告)号：US07532210B2

公开(公告)日：2009-05-12

申请号：US11311847

申请日：2005-12-19

申请人： Lomg Kuan Chen ,  Eddy G. Chen ,  Chih-Sheng Chang ,  Sz Hsiao Chen ,  Tsau Hua Hsieh ,  Jia-Pang Pang

发明人： Lomg Kuan Chen ,  Eddy G. Chen ,  Chih-Sheng Chang ,  Sz Hsiao Chen ,  Tsau Hua Hsieh ,  Jia-Pang Pang

IPC分类号： G06F3/038 ,  G09G3/36

CPC分类号： G09G3/3648 ,  G09G2310/0251 ,  G09G2310/061 ,  G09G2320/0252 ,  G09G2320/0261

摘要： A driving method for an active matrix liquid crystal display panel includes the following steps. First, a frame period is divided into a display period (t1) and a black insertion period (tr). A gray-scale voltage is generated according to a desired corresponding light transmittance of each pixel of the liquid crystal display panel; and during the display period, the gray-scale voltage is supplied to a corresponding pixel electrode of the liquid crystal display panel. Then during the black insertion period, a restoring voltage Vh is supplied to the pixel electrode, so that the pixel is returned to an initial black state. Accordingly, the quality of motion pictures of the liquid crystal display panel is good.

摘要翻译： 有源矩阵液晶显示面板的驱动方法包括以下步骤。 首先，帧周期被分为显示周期（t1）和黑插入周期（tr）。 根据液晶显示面板的每个像素的期望的对应的透光率产生灰度电压; 并且在显示期间，将灰度电压提供给液晶显示面板的对应像素电极。 然后在黑插入期间，将恢复电压Vh提供给像素电极，使得像素返回到初始黑色状态。 因此，液晶显示面板的运动画面的质量良好。

公开(公告)号：US07468305B2

公开(公告)日：2008-12-23

申请号：US11414980

申请日：2006-05-01

申请人： Michael Yu ,  Chih-Ping Chao ,  Chih-Sheng Chang ,  Chun-Hong Chen

发明人： Michael Yu ,  Chih-Ping Chao ,  Chih-Sheng Chang ,  Chun-Hong Chen

IPC分类号： H01L21/331

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of decoupling the formation of LDD and pocket regions is provided. The method includes providing a semiconductor chip including active regions, forming gate structures in the active regions, forming N-LDD regions on the semiconductor chip using an N-LDD mask, forming N-Pocket regions on the semiconductor chip using an N-Pocket mask, forming P-LDD regions on the semiconductor chip using a P-LDD mask, and forming P-Pocket regions on the semiconductor chip using a P-Pocket mask.

摘要翻译： 提供了一种解耦LDD和口袋区域的方法。 该方法包括提供包括有源区的半导体芯片，在有源区中形成栅结构，使用N-LDD掩模在半导体芯片上形成N-LDD区，使用N-Pocket掩模在半导体芯片上形成N-口袋区 使用P-LDD掩模在半导体芯片上形成P-LDD区域，并使用P-Pocket掩模在半导体芯片上形成P-Pocket区域。

公开(公告)号：US07462560B2

公开(公告)日：2008-12-09

申请号：US11161649

申请日：2005-08-11

申请人： Nien-Chung Chiang ,  Chih-Sheng Chang ,  Chun-Hsing Tung ,  Yi-Tyng Wu ,  Huai-Hsuan Tsai ,  Chi-Rong Lin

发明人： Nien-Chung Chiang ,  Chih-Sheng Chang ,  Chun-Hsing Tung ,  Yi-Tyng Wu ,  Huai-Hsuan Tsai ,  Chi-Rong Lin

IPC分类号： H01L21/44

CPC分类号： C23C14/165 ,  C23C14/541 ,  G02B5/08

摘要： A process of physical vapor depositing mirror layer with improved reflectivity is disclosed. A wafer is loaded into a PVD tool comprising a degas chamber, a Ti/TiN sputter deposition chamber, a cooling chamber, and an aluminum sputter deposition chamber. A wafer degas process is first performed within the degas chamber. The wafer is then transferred to the Ti/TiN sputter deposition chamber and deposition sputtering a layer of titanium onto the wafer. The wafer is transferred to the cooling chamber and gas cooling the wafer temperature down to 40-50° C. The wafer is then transferred to the aluminum sputter deposition chamber and deposition sputtering a layer of aluminum onto the wafer at 40-50° C. with a backside gas turned off. The deposited layer of aluminum over the wafer has a reflectivity of about 0.925 at wavelength of around 380 nm.

摘要翻译： 公开了一种具有改进的反射率的物理气相沉积镜层的方法。 将晶片装载到包括脱气室，Ti / TiN溅射沉积室，冷却室和铝溅射沉积室的PVD工具中。 首先在脱气室内执行晶片脱气工艺。 然后将晶片转移到Ti / TiN溅射沉积室，并将一层钛沉积到晶片上。 将晶片转移到冷却室，并将晶片温度降至40-50℃。然后将晶片转移到铝溅射沉积室，并在40-50℃下将一层铝沉积到晶片上。 背面气体关闭。 在晶片上沉积的铝层在约380nm的波长处具有约0.925的反射率。

公开(公告)号：US20070254447A1

公开(公告)日：2007-11-01

申请号：US11414980

申请日：2006-05-01

申请人： Michael Yu ,  Chih-Ping Chao ,  Chih-Sheng Chang ,  Chun-Hong Chen

发明人： Michael Yu ,  Chih-Ping Chao ,  Chih-Sheng Chang ,  Chun-Hong Chen

IPC分类号： H01L21/8222

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of decoupling the formation of LDD and pocket regions is provided. The method includes providing a semiconductor chip including active regions, forming gate structures in the active regions, forming N-LDD regions on the semiconductor chip using an N-LDD mask, forming N-Pocket regions on the semiconductor chip using an N-Pocket mask, forming P-LDD regions on the semiconductor chip using a P-LDD mask, and forming P-Pocket regions on the semiconductor chip using a P-Pocket mask.

摘要翻译： 提供了一种解耦LDD和口袋区域的方法。 该方法包括提供包括有源区的半导体芯片，在有源区中形成栅结构，使用N-LDD掩模在半导体芯片上形成N-LDD区，使用N-Pocket掩模在半导体芯片上形成N-口袋区 使用P-LDD掩模在半导体芯片上形成P-LDD区域，并使用P-Pocket掩模在半导体芯片上形成P-Pocket区域。

公开(公告)号：US20070037393A1

公开(公告)日：2007-02-15

申请号：US11161649

申请日：2005-08-11

申请人： Nien-Chung Chiang ,  Chih-Sheng Chang ,  Chun-Hsing Tung ,  Yi-Tyng Wu ,  Huai-Hsuan Tsai ,  Chi-Rong Lin

发明人： Nien-Chung Chiang ,  Chih-Sheng Chang ,  Chun-Hsing Tung ,  Yi-Tyng Wu ,  Huai-Hsuan Tsai ,  Chi-Rong Lin

IPC分类号： H01L21/44

CPC分类号： C23C14/165 ,  C23C14/541 ,  G02B5/08

摘要： A process of physical vapor depositing mirror layer with improved reflectivity is disclosed. A wafer is loaded into a PVD tool comprising a degas chamber, a Ti/TiN sputter deposition chamber, a cooling chamber, and an aluminum sputter deposition chamber. A wafer degas process is first performed within the degas chamber. The wafer is then transferred to the Ti/TiN sputter deposition chamber and deposition sputtering a layer of titanium onto the wafer. The wafer is transferred to the cooling chamber and gas cooling the wafer temperature down to 40-50° C. The wafer is then transferred to the aluminum sputter deposition chamber and deposition sputtering a layer of aluminum onto the wafer at 40-50° C. with a backside gas turned off. The deposited layer of aluminum over the wafer has a reflectivity of about 0.925 at wavelength of around 380 nm.

摘要翻译： 公开了一种具有改进的反射率的物理气相沉积镜层的方法。 将晶片装载到包括脱气室，Ti / TiN溅射沉积室，冷却室和铝溅射沉积室的PVD工具中。 首先在脱气室内执行晶片脱气工艺。 然后将晶片转移到Ti / TiN溅射沉积室，并将一层钛沉积到晶片上。 将晶片转移到冷却室，并将晶片温度降至40-50℃。然后将晶片转移到铝溅射沉积室，并在40-50℃下将一层铝沉积到晶片上。 背面气体关闭。 在晶片上沉积的铝层在约380nm的波长处具有约0.925的反射率。

公开(公告)号：US07129547B2

公开(公告)日：2006-10-31

申请号：US10971624

申请日：2004-10-22

申请人： Yin-Pin Wang ,  Chih-Sheng Chang

发明人： Yin-Pin Wang ,  Chih-Sheng Chang

IPC分类号： H01L29/78

CPC分类号： H01L29/66545 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： A method of fabricating a MOSFET device featuring a raised source/drain structure on a heavily doped source/drain region as well as on a portion of a lightly doped source/drain (LDD), region, after removal of an insulator spacer component, has been developed. After formation of an LDD region a composite insulator spacer, comprised of an underlying silicon oxide spacer component and an overlying silicon nitride spacer component, is formed on the sides of a gate structure. Formation of a heavily doped source/drain is followed by removal of the silicon nitride spacer resulting in recessing of, and damage formation to, the heavily doped source/drain region, as well as recessing of the gate structure. Removal of a horizontal component of the silicon oxide spacer component results in additional recessing of the heavily doped source/drain region, and of the gate structure. A selective epitaxial growth procedure is then used to form a raised, single crystalline silicon structure on the recessed and damaged heavily doped source/drain and LDD regions, while a polycrystalline silicon structure is grown on the underlying recessed gate structure. Metal silicide is then formed on the raised, single crystalline silicon structure and on the polycrystalline silicon structure.

摘要翻译： 一种制造MOSFET器件的方法，其特征在于在重掺杂的源极/漏极区域上以及在去除绝缘体隔离器部件之后的轻掺杂源极/漏极（LDD）区域的一部分上具有升高的源极/漏极结构， 已经开发 在LDD区域的形成之后，在栅极结构的侧面上形成由下面的氧化硅间隔物组分和上覆的氮化硅间隔物组分组成的复合绝缘体间隔物。 重掺杂源极/漏极的形成之后是去除氮化硅间隔物，导致重掺杂源极/漏极区的凹陷和损伤形成以及栅极结构的凹陷。 去除氧化硅间隔物组分的水平分量导致重掺杂的源极/漏极区域和栅极结构的额外的凹陷。 然后使用选择性外延生长方法在凹陷和损坏的重掺杂源/漏极和LDD区上形成升高的单晶硅结构，同时在下面的栅极栅极结构上生长多晶硅结构。 然后在凸起的单晶硅结构和多晶硅结构上形成金属硅化物。

公开(公告)号：US20050258507A1

公开(公告)日：2005-11-24

申请号：US10851021

申请日：2004-05-21

申请人： Bor-Min Tseng ,  Chih-Sheng Chang

发明人： Bor-Min Tseng ,  Chih-Sheng Chang

IPC分类号： H01F17/00 ,  H01L21/822 ,  H01L23/522 ,  H01L27/06 ,  H01L27/08 ,  H02M1/12

CPC分类号： H01L27/0688 ,  H01F21/00 ,  H01F2017/008 ,  H01L21/8221 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic device including, in one embodiment, a plurality of active devices located at least partially in a substrate, at least one dielectric layer located over the plurality of active devices, and an inductor located over the dielectric layer. At least one of the plurality of active devices is located within a columnar region having a cross-sectional shape substantially conforming to a perimeter of the inductor. The at least one of the plurality of active devices may be biased based on a desired Q factor of the inductor or and/or an operating frequency of the microelectronic device.

摘要翻译： 在一个实施例中，微电子器件包括至少部分地位于衬底中的多个有源器件，位于多个有源器件上方的至少一个电介质层，以及位于电介质层上方的电感器。 多个有源器件中的至少一个位于具有基本上符合电感器的周边的横截面形状的柱状区域内。 多个有源器件中的至少一个可以基于电感器的期望Q因子或/或微电子器件的工作频率而偏置。

公开(公告)号：US20050117588A1

公开(公告)日：2005-06-02

申请号：US10918977

申请日：2004-08-16

申请人： Kuo-Kun Tseng ,  Chia-Ren Hsu ,  Ying-Dar Lin ,  Chien Chen ,  Chih-Sheng Chang ,  Po-Cheng Wu ,  Wumin Chen ,  Chiuan-Yu Wei

发明人： Kuo-Kun Tseng ,  Chia-Ren Hsu ,  Ying-Dar Lin ,  Chien Chen ,  Chih-Sheng Chang ,  Po-Cheng Wu ,  Wumin Chen ,  Chiuan-Yu Wei

IPC分类号： H04L29/12 ,  H04L12/28

CPC分类号： H04L29/12367 ,  H04L29/12009 ,  H04L29/12924 ,  H04L61/2514 ,  H04L61/6063

摘要： A system for network address port translation. The system comprises a storage device and a translation module. The storage device stores a plurality of private address tables and a private port table, wherein each private address table and private port table comprises at least one entry, and each entry is assigned an index number. The translation module, connected to the storage device, receives a private IP address and a private port number, wherein the private IP address comprises a plurality of private address subsets, stores the private address subsets and private port number as entries in the private address tables and the private port table, respectively, and translates the private IP address and port number to and from a public port number, wherein the public port number comprises a plurality of public port subsets corresponding to the index numbers in the private address tables and the private port table.

摘要翻译： 一种用于网络地址端口转换的系统。 该系统包括存储装置和翻译模块。 存储装置存储多个私有地址表和专用端口表，其中每个专用地址表和专用端口表包括至少一个条目，并且每个条目被分配索引号。 连接到存储设备的翻译模块接收私有IP地址和专用端口号，其中专用IP地址包括多个私有地址子集，将专用地址子集和专用端口号作为条目存储在专用地址表中 和专用端口表，并且将私有IP地址和端口号转换为公共端口号，其中公共端口号包括与私有地址表中的索引号对应的多个公共端口子集和私有端口号 端口表。

公开(公告)号：US06483841B1

公开(公告)日：2002-11-19

申请号：US09260073

申请日：1999-03-02

申请人： Chung-Ju Chang ,  Huai-Chih Ma ,  Chih-Sheng Chang ,  Jiunn-Bin Chen

发明人： Chung-Ju Chang ,  Huai-Chih Ma ,  Chih-Sheng Chang ,  Jiunn-Bin Chen

IPC分类号： H04L1256

CPC分类号： H04L29/06 ,  H04L49/3027 ,  H04L49/351 ,  H04L69/22

摘要： The present invention is to provide an Ethernet switch fabric controller requiring output port buffer unit of less capacity while still working with an Ethernet switch to smoothly forward the packet from each input port of the Ethernet switch to an output port corresponding to the packet header at the input port. It is featured by the use of proper number of temporary buffer units each of proper length, and output port buffer unit of proper length.

摘要翻译： 本发明是提供一种以太网交换结构控制器，其需要具有较少容量的输出端口缓冲单元，同时仍然使用以太网交换机来将分组从以太网交换机的每个输入端口平滑地转发到对应于分组报头的输出端口 输入端口。 它使用适当长度的适当数量的临时缓冲单元和适当长度的输出端口缓冲单元。

公开(公告)号：US20230091820A1

公开(公告)日：2023-03-23

申请号：US17888496

申请日：2022-08-16

申请人： Chih-Sheng Chang

发明人： Chih-Sheng Chang

IPC分类号： C04B41/52 ,  C04B35/626 ,  C04B41/45 ,  C04B41/50 ,  C04B41/87 ,  C04B41/89

摘要： The present invention provides an antimicrobial ceramic tile and manufacturing method thereof. A manufacturing method of an antimicrobial ceramic tile comprises: grinding soils into slurries; drying the slurries into powders by hot air; pressing the powders into a green body through a molding machine; dotting or spraying or showering a glaze slurry on the surface of the green body to form an engobe; dotting the glaze slurry on the engobe to form a ground glaze; mixing a surface glaze and an antimicrobial material into an antimicrobial glaze in a weight ratio of 100:5˜10; grinding water and the antimicrobial glaze into the antimicrobial glaze in a weight ratio of 5˜6:4˜5; and dotting antimicrobial glaze on the ground glaze; finally, rapidly firing the ceramic tile and the antimicrobial glaze into an antimicrobial ceramic tile.