知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

97 条记录 (耗时 0.031 秒)

    Single wire bus for connecting devices and methods of operating the same
    52.
    发明授权
    Single wire bus for connecting devices and methods of operating the same 有权
    用于连接设备的单线总线及其操作方法

    公开(公告)号：US07181557B1

    公开(公告)日：2007-02-20

    申请号：US10932347

    申请日：2004-09-01

    申请人： Ohad Falik ,  Victor Flachs

    发明人： Ohad Falik ,  Victor Flachs

    IPC分类号： G06F13/00 ,  G06F13/42

    CPC分类号： G06F13/4286

    摘要： A master/slave system architecture including a single wire bus and master device and bus interface coupled to the bus. The system further includes slave devices having respective bus interfaces coupled to the bus. The system further includes a communication protocol implemented over the single wire bus and employed by the master and the slave devices. The protocol includes bus transactions for communicating between the master and the slave devices. The communication protocol further includes Master Slave Operational Interface (MSOI) that includes repertoire of functions properties stored in the master device, whereby, the master can communicate with any slave device that supports functions properties that belong to the repertoire of functions properties, using the bus transactions, substantially without need of retrofit.

    摘要翻译： 主/从系统架构包括单线总线和主设备以及总线接口。 该系统还包括具有耦合到总线的相应总线接口的从设备。 该系统还包括通过单线总线实现并由主设备和从设备使用的通信协议。 该协议包括用于在主设备和从设备之间通信的总线事务。 通信协议还包括主从操作接口（MSOI），其包括存储在主设备中的功能属性的所有内容，由此，主设备可以与支持功能属性功能属性的任何从设备通信，使用总线 交易，基本上不需要改装。

    Methods and arrangements for capturing runtime information
    53.
    发明授权
    Methods and arrangements for capturing runtime information 有权
    捕获运行时信息的方法和安排

    公开(公告)号：US07177782B2

    公开(公告)日：2007-02-13

    申请号：US10871848

    申请日：2004-06-18

    申请人： Ohad Falik ,  Joseph Wayne Freeman ,  Isaac Karpel ,  James S. Rutledge ,  Randall Scott Springfield

    发明人： Ohad Falik ,  Joseph Wayne Freeman ,  Isaac Karpel ,  James S. Rutledge ,  Randall Scott Springfield

    IPC分类号： G06F15/00 ,  G06F12/00

    CPC分类号： G06F11/348 ,  G06F11/0778 ,  G06F11/1666 ,  G06F11/2015

    摘要： Methods and arrangements for capturing information related to operational conditions are disclosed. Embodiments include volatile memory to quickly record operational parameters via, e.g., basic input output system (BIOS) code, system management interrupt (SMI) code and/or executing applications. Many embodiments provide an alternative power source and a voltage switch to protect against loss of the information between storage in the volatile memory and storage in the non-volatile memory. Some embodiments include a read controller that provides access to the volatile memory when primary power is available. The read controller may also offer direct access to the non-volatile memory in case of a catastrophic failure that renders the processing device substantially non-functional. Further embodiments include a second processing device to generate a usage model and/or to perform diagnostics with the operational parameters.

    摘要翻译： 公开了捕获与操作条件有关的信息的方法和布置。 实施例包括通过例如基本输入输出系统（BIOS）代码，系统管理中断（SMI）代码和/或执行应用程序来快速记录操作参数的易失性存储器。 许多实施例提供了替代电源和电压开关，以防止在易失性存储器中的存储器和非易失性存储器中的存储之间的信息丢失。 一些实施例包括在主电源可用时提供对易失性存储器的访问的读取控制器。 在导致处理设备基本上不起作用的灾难性故障的情况下，读控制器还可以提供对非易失性存储器的直接访问。 另外的实施例包括用于生成使用模型和/或使用操作参数执行诊断的第二处理装置。

    Method and apparatus for determining the temperature of a junction using voltage responses of the junction and a correction factor
    54.
    发明授权
    Method and apparatus for determining the temperature of a junction using voltage responses of the junction and a correction factor 失效
    用于使用结的电压响应确定结的温度的方法和装置以及校正因子

    公开(公告)号：US07170275B1

    公开(公告)日：2007-01-30

    申请号：US11085828

    申请日：2005-03-21

    申请人： Ohad Falik

    发明人： Ohad Falik

    IPC分类号： G01R31/02 ,  G01R27/02 ,  G01N27/00

    CPC分类号： G01K15/00 ,  G01K7/01

    摘要： Method and system for periodically measuring the junction temperature of a semiconductor device. The junction is excited by at least two sequential predetermined currents of different magnitudes. The voltage response of the junction to the at least two currents is measured and the temperature of the junction is calculated, while substantially canceling ohmic effects, by using the voltage response and a correction factor. Whenever desired, the junction is excited by a set of at least four sequential different currents having known ratios. The voltage response to the set is measured and the correction factor is calculated by using each voltage response to the set.

    摘要翻译： 用于周期性测量半导体器件的结温的方法和系统。 该结被不同幅度的至少两个顺序的预定电流激发。 测量结到至少两个电流的电压响应，并且通过使用电压响应和校正因子来计算结点的温度，同时基本上消除欧姆效应。 无论何时，通过具有已知比例的至少四个顺序的不同电流的一组激发该结。 测量对该组的电压响应，并通过使用对该组的每个电压响应来计算校正因子。

    A/D converter with comparators and low-power detection mode for resistive matrix keyboards
    55.
    发明授权
    A/D converter with comparators and low-power detection mode for resistive matrix keyboards 有权
    具有比较器的A / D转换器和用于电阻矩阵键盘的低功耗检测模式

    公开(公告)号：US07161505B1

    公开(公告)日：2007-01-09

    申请号：US10929731

    申请日：2004-08-30

    申请人： Ohad Falik ,  Victor Flachs

    发明人： Ohad Falik ,  Victor Flachs

    IPC分类号： H03M11/00

    CPC分类号： H03M11/02 ,  H03M11/20

    摘要： An apparatus and method is disclosed for providing a fast, low power consumption, detection of at least one depressed key in a resistive matrix keyboard. The common contact of each row of a resistive matrix is connected to a first input of each of a plurality of analog/digital comparators capable of switching between high and low voltage states. A common predetermined reference voltage is applied to a second input of each analog/digital comparator using a digital to analog converter. The output of a analog/digital comparator is in a first state if the voltage level applied to the first input is higher than the reference voltage, and in a second state if the voltage level applied to the first input is lower than the reference voltage. The reference voltage is varied to identify which analog/digital comparator has experienced a change of state.

    摘要翻译： 公开了一种用于提供对电阻矩阵键盘中的至少一个按键的快速，低功耗检测的装置和方法。 电阻矩阵的每行的公共接触连接到能够在高电压状态和低电压状态之间切换的多个模拟/数字比较器中的每一个的第一输入。 使用数模转换器将共同的预定参考电压施加到每个模拟/数字比较器的第二输入。 如果施加到第一输入的电压电平高于参考电压，则模拟/数字比较器的输出处于第一状态，并且在施加到第一输入的电压电平低于参考电压的情况下处于第二状态。 改变参考电压以识别哪个模拟/数字比较器经历了状态的改变。

    Circuit that implements semaphores in a multiprocessor environment without reliance on atomic test and set operations of the processor cores
    56.
    发明授权
    Circuit that implements semaphores in a multiprocessor environment without reliance on atomic test and set operations of the processor cores 失效
    在多处理器环境中实现信号量的电路，而不依赖于原子测试和处理器内核的设置操作

    公开(公告)号：US06263425B1

    公开(公告)日：2001-07-17

    申请号：US08889796

    申请日：1997-07-08

    申请人： Ohad Falik

    发明人： Ohad Falik

    IPC分类号： G06F952

    CPC分类号： G06F9/52

    摘要： A hardware semaphore is one bit wide. A first hardware circuit detects one of the processes is writing a new value to the semaphore and forces the hardware semaphore to the new value written. A plurality of second hardware circuits are provided. Each second hardware circuit is associated with a separate one of the plurality of processes. Each of the particular second hardware circuit includes a detecting circuit that detects the processor with which the particular second hardware circuit is associated is attempting to write the new value to the semaphore. A circuit responsive to the detecting circuit provides the current value of the semaphore, before the write, to an output of the second particular hardware circuit.

    摘要翻译： 硬件信号量有一位宽。 第一个硬件电路检测到一个进程正在向信号量写入一个新值，并强制硬件信号量写入新值。 提供多个第二硬件电路。 每个第二硬件电路与多个处理中的单独的一个进行关联。 特定第二硬件电路中的每一个包括检测电路，其检测特定的第二硬件电路与哪个处理器相关联的是尝试将新值写入信号量。 响应于检测电路的电路在写入之前将信号量的当前值提供给第二特定硬件电路的输出。

    Processor core which provides a linear extension of an addressable memory space
    58.
    发明授权
    Processor core which provides a linear extension of an addressable memory space 失效
    处理器内核提供可寻址存储空间的线性扩展

    公开(公告)号：US5566308A

    公开(公告)日：1996-10-15

    申请号：US248769

    申请日：1994-05-25

    申请人： Chaim Bendelac ,  Dan Biran ,  Ohad Falik ,  Gadi Erlich ,  Jonathan Levy ,  Gideon Intrater

    发明人： Chaim Bendelac ,  Dan Biran ,  Ohad Falik ,  Gadi Erlich ,  Jonathan Levy ,  Gideon Intrater

    IPC分类号： G06F9/32 ,  G06F9/355 ,  G06F12/00

    CPC分类号： G06F9/342 ,  G06F9/32 ,  G06F9/321

    摘要： A processor core for provides a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. A N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2.sup.x times more memory locations than 2.sup.N. Two other registers each hold a portion of an data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.

    摘要翻译： 处理器核心，用于提供微处理器的可寻址存储空间的线性扩展，同时具有最小的附加硬件和软件复杂性。 N + x位指针寄存器（例如程序计数器）保存N + x位指令地址。 N + x位指令地址向执行单元提供指向由执行单元处理的存储器中的指令的指针。 编码器将N + x位地址编码为N + x位地址的N位编码。 因此，处理器核可以处理比2N多两倍的存储单元。 另外两个寄存器分别保存数据地址的一部分（即指向要操作的存储器中的基准的指针）。 地址前缀将两个寄存器中地址的部分连接起来形成数据地址。 因此，地址由存储在多个寄存器中的数据地址的部分形成，而不对这些部分执行任何算术。