公开(公告)号：US20080307163A1

公开(公告)日：2008-12-11

申请号：US11758802

申请日：2007-06-06

申请人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

IPC分类号： G06F12/00

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C11/5671

摘要： A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2n bits, n is a positive integer. The method for accessing memory includes the following steps: Firstly, threshold voltages of the storage are defined into 2n level respectively, wherein each of the 2n level corresponds to a storage status of n bits, and most significant bits of the storage statuses which level 0 to level 2n/2−1 correspond to are different from most significant bits of the storage statuses which level 2n/2 to level 2n−1 correspond to. Next, a target data is divided into n portions and the divided target data is written into n temporary memories respectively. Then, n bits of the target data are written into the multi-level cell. Each of the n bits data is collected from each of the n temporary memories.

公开(公告)号：US07426139B2

公开(公告)日：2008-09-16

申请号：US11555849

申请日：2006-11-02

申请人： Wen Chiao Ho ,  Chin Hung Chang ,  Kuen-Long Chang ,  Chun Hsiung Hung

发明人： Wen Chiao Ho ,  Chin Hung Chang ,  Kuen-Long Chang ,  Chun Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C2211/5621

摘要： A method for operating a multi-level cell (“MLC”) memory array of an integrated circuit (“IC”) programs first data into a first plurality of MLCs in the MLC memory array at a first programming level. Threshold voltages for the first plurality of MLCs are sensed, and an adjust code is set according to the threshold voltages. Second data is programmed into a second plurality of MLCs in the MLC memory array at a second programming level, the second plurality of MLCs having a program-verify value set according to the adjust code. In a further embodiment, a reference voltage for reading the second plurality of MLCs is set according to the adjust code.

摘要翻译： 用于操作集成电路（“IC”）的多级单元（“MLC”）存储器阵列的方法在第一编程级将第一数据编程到MLC存储器阵列中的第一多个MLC中。 感测第一多个MLC的阈值电压，并且根据阈值电压设置调整代码。 第二数据在第二编程级别被编程到MLC存储器阵列中的第二多个MLC中，第二多个MLC具有根据调整代码设置的程序验证值。 在另一实施例中，根据调整代码来设置用于读取第二多个MLC的参考电压。

公开(公告)号：US07382656B2

公开(公告)日：2008-06-03

申请号：US11552293

申请日：2006-10-24

申请人： Wen Chiao Ho ,  Yi Chun Shih ,  Chin Hung Chang ,  Chun Hsiung Hung

发明人： Wen Chiao Ho ,  Yi Chun Shih ,  Chin Hung Chang ,  Chun Hsiung Hung

IPC分类号： G11C11/34

CPC分类号： G11C16/3468

摘要： A page mode program sequence is described that includes first and second bias applying cycles. In the first cycle, a program bias is applied to a first part of a page of memory cells, while a program verify bias is applied to, and data is sensed from, a second part of the page. In this manner, a first part of the page is programmed, while a second part of the page is verified. This operation is followed by a second bias applying cycle, in which a program bias is applied to the second part of the page, while a program verify bias is applied to, and data is sensed from, the first part of the page.

摘要翻译： 描述了包括第一和第二偏置施加周期的页面模式程序序列。 在第一周期中，程序偏差被施加到一页存储器单元的第一部分，同时程序验证偏差被施加到页面的第二部分并且从该页面的第二部分感测数据。 以这种方式，页面的第一部分被编程，而页面的第二部分被验证。 该操作之后是第二偏置施加周期，其中将程序偏置施加到页面的第二部分，同时将程序验证偏差施加到页面的第一部分并且从页面的第一部分感测数据。

公开(公告)号：US20080109697A1

公开(公告)日：2008-05-08

申请号：US11727256

申请日：2007-03-26

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Chun-Hsiung Hung ,  Kuen-Long Chang

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Chun-Hsiung Hung ,  Kuen-Long Chang

IPC分类号： H03M13/00

CPC分类号： H03M13/13 ,  G06F11/1068 ,  H03M13/03 ,  H03M13/3776

摘要： A method for checking reading errors of a memory includes receiving a first data fragment and accordingly generating a first ECC and a first count index; writing the first data fragment, the first ECC and the first count index into a memory; reading the first data fragment from the memory as a second data fragment, generating a second ECC and second count index according to the second data fragment; determining whether the first count index and second count index are equal; determining whether the first ECC and the second ECC are equal; and outputting the second data fragment when the first count index is equal to the second count index and the first ECC is equal to the second ECC.

摘要翻译： 用于检查存储器的读取错误的方法包括接收第一数据片段并相应地生成第一ECC和第一计数索引; 将第一数据片段，第一ECC和第一计数索引写入存储器; 从所述存储器读取所述第一数据片段作为第二数据片段，根据所述第二数据片段生成第二ECC和第二计数索引; 确定第一计数指数和第二计数指数是否相等; 确定第一ECC和第二ECC是否相等; 并且当所述第一计数索引等于所述第二计数索引并且所述第一ECC等于所述第二ECC时，输出所述第二数据片段。

公开(公告)号：US07180780B1

公开(公告)日：2007-02-20

申请号：US11281181

申请日：2005-11-17

申请人： Wen Chiao Ho ,  Chin Hung Chang ,  Kuen Long Chang ,  Chun Hsiung Hung

发明人： Wen Chiao Ho ,  Chin Hung Chang ,  Kuen Long Chang ,  Chun Hsiung Hung

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3459

摘要： The present invention provides a novel method in altering the sequence of multi-level-cell programming in a multi-bit-cell of a nitride trapping memory cell that reduces or eliminates voltage threshold shifts between program steps while avoiding the suppression in the duration of a read window caused by a complementary bit disturbance. In a first embodiment, the present invention programs the multi-level cell in a multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a first program level (level1) and a second program level (level2) to level 1, and programming the second program level from the first program level. In a second embodiment, the present invention programs the multi-level cell in the multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a second program level (level2), and programming a first program level (level 1).

摘要翻译： 本发明提供了一种在氮化物俘获存储器单元的多位单元中改变多电平单元编程的顺序的新颖方法，其减少或消除了程序步骤之间的电压阈值偏移，同时避免了在 读取窗口由互补位干扰引起。 在第一实施例中，本发明按照以下顺序在具有四位的多位单元中编程多电平单元：编程第三程序级（level3），编程第一程序级（level1）和第二程序 级别（level2）到级别1，并从第一程序级别编程第二程序级别。 在第二实施例中，本发明按照以下顺序对具有四位的多比特单元中的多电平单元进行编程：编程第三程序级（level3），编程第二程序级（level2），并编程 第一程序级（1级）。

公开(公告)号：US06845052B1

公开(公告)日：2005-01-18

申请号：US10250040

申请日：2003-05-30

申请人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Liang Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

发明人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Liang Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

IPC分类号： G11C7/06 ,  G11C7/14 ,  G11C16/28 ,  G11C7/02

CPC分类号： G11C7/14 ,  G11C7/062 ,  G11C16/28 ,  G11C2207/2227

摘要： The present invention provides a dual reference cell sensing scheme for non-volatile memory. A high voltage reference cell and a low voltage reference cell are individually coupled to two sense amplifiers for providing two distinct reference voltages for comparison against the memory cell voltage. The output of the two sense amplifiers is further connected to a second stage sense amplifier to determine the status of the memory. The dual reference cell sensing scheme provides an increased sensing window which increases performance under low voltage application. The dual reference cell sensing scheme can be implemented by either voltage-based, current-based, or ground.

摘要翻译： 本发明提供了一种用于非易失性存储器的双参考单元感测方案。 高电压参考单元和低电压参考单元分别耦合到两个读出放大器，用于提供用于与存储单元电压进行比较的两个不同的参考电压。 两个读出放大器的输出进一步连接到第二级读出放大器以确定存储器的状态。 双参考电池感测方案提供增加的感测窗口，其在低电压应用下增加性能。 双参考电池感测方案可以通过基于电压，基于电流或接地来实现。

公开(公告)号：US06665216B1

公开(公告)日：2003-12-16

申请号：US10202245

申请日：2002-07-23

申请人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Laing Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

发明人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Laing Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

IPC分类号： G11C700

CPC分类号： G11C16/28 ,  G11C7/062

摘要： A system for reading data in a memory cell includes three comparators, each of which has two inputs. A first reference cell having a low reference voltage is coupled to one input of the first comparator. A second reference cell having a high reference voltage is coupled to one input of the second comparator. A memory cell having a memory cell voltage is coupled to the other input of the first and second comparators. One input of the third comparator is coupled to the first comparator's output signal, which includes a difference voltage between the memory cell voltage and the low reference voltage. The other input of the third comparator is coupled to the second comparator's output signal, which includes a difference voltage between the memory cell voltage and the high reference voltage. A method and apparatus for reading data in a memory cell also are described.

摘要翻译： 用于读取存储器单元中的数据的系统包括三个比较器，每个比较器具有两个输入。 具有低参考电压的第一参考单元耦合到第一比较器的一个输入端。 具有高参考电压的第二参考单元耦合到第二比较器的一个输入端。 具有存储单元电压的存储单元耦合到第一和第二比较器的另一个输入端。 第三比较器的一个输入耦合到第一比较器的输出信号，其包括存储单元电压和低参考电压之间的差电压。 第三比较器的另一输入端耦合到第二比较器的输出信号，其包括存储单元电压和高参考电压之间的差电压。 还描述了一种用于在存储器单元中读取数据的方法和装置。

公开(公告)号：US08176373B2

公开(公告)日：2012-05-08

申请号：US13042910

申请日：2011-03-08

申请人： Chun-Hsiung Hung ,  Wen-Chiao Ho

发明人： Chun-Hsiung Hung ,  Wen-Chiao Ho

IPC分类号： G11C29/00

CPC分类号： G11C8/12 ,  G11C29/808

摘要： A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block.

摘要翻译： 预编码装置包括第一存储器电路，地址解码器和替代逻辑电路。 第一存储器电路包括多个存储器块，并且在东部包括替换块。 存储器块由多个相应的物理地址指向。 替换块由替换地址指向。 地址解码器解码输入地址以提供预代码地址。 替代逻辑电路查找地址映射表，其将物理地址中的缺陷物理地址映射到替换地址，以在预代码地址对应于缺陷物理地址时将前缀地址映射到替换地址。 替代逻辑电路相应地将代码前数据预编码到替换块。

公开(公告)号：US07965551B2

公开(公告)日：2011-06-21

申请号：US11703115

申请日：2007-02-07

申请人： Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C11/34

CPC分类号： G11C7/18 ,  G11C7/02

摘要： A method for metal bit line arrangement is applied to a virtual ground array memory having memory cell blocks. Each memory cell block has memory cells and m metal bit lines, wherein m is a positive integer. The method includes the following steps. First, one of the memory cells is selected as a target memory cell. When the target memory cell is being read, the metal bit line electrically connected to a drain of the target memory cell is a drain metal bit line, and the metal bit line electrically connected to a source is a source metal bit line. Next, a classification of whether the other metal bit lines are charged up when the target memory cell is being read is made. Thereafter, the m metal bit lines are arranged such that charged up metal bit lines are not adjacent to the source metal bit line.

摘要翻译： 一种用于金属位线布置的方法被应用于具有存储单元块的虚拟地阵列存储器。 每个存储单元块具有存储单元和m个金属位线，其中m是正整数。 该方法包括以下步骤。 首先，选择一个存储单元作为目标存储单元。 当读出目标存储单元时，与目标存储单元的漏极电连接的金属位线是漏极金属位线，与源极电连接的金属位线是源极金属位线。 接着，对目标存储单元进行读取时，分类其他金属位线是否被充电。 此后，m个金属位线布置成使得带电的金属位线不与源极金属位线相邻。

公开(公告)号：US20100027339A1

公开(公告)日：2010-02-04

申请号：US12182245

申请日：2008-07-30

申请人： Wen-Chiao HO ,  Chin-Hung CHANG ,  Kuen-Long CHANG ,  Chun-Hsiung HUNG

发明人： Wen-Chiao HO ,  Chin-Hung CHANG ,  Kuen-Long CHANG ,  Chun-Hsiung HUNG

IPC分类号： G11C16/04 ,  G11C7/00

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5646 ,  G11C2216/14

摘要： A page buffer and method of programming and reading a memory are provided. The page buffer includes a first latch, a second latch, a data change unit and a program control unit. The first latch includes a first terminal for loading data of the lower page and the upper page. The second latch includes a first terminal for storing the data of the lower page and the upper page from the first latch. The data change unit is coupled to a second terminal of the first latch for changing a voltage of the second terminal of the first latch to a low level. The program control unit is coupled to the first terminal of the second latch and the cells, and controlled by the voltage of the first terminal of the first latch for respectively programming the data of the lower page and the upper page to a target cell.

摘要翻译： 提供了一种页面缓冲器和编程和读取存储器的方法。 页面缓冲器包括第一锁存器，第二锁存器，数据改变单元和程序控制单元。 第一锁存器包括用于加载下页和上页的数据的第一终端。 第二锁存器包括用于存储来自第一锁存器的下页数据和上页数据的第一终端。 数据改变单元耦合到第一锁存器的第二端子，用于将第一锁存器的第二端子的电压改变到低电平。 程序控制单元耦合到第二锁存器和单元的第一端子，并且由第一锁存器的第一端子的电压控制，以分别将下页数据和上部页面的数据编程到目标单元。