公开(公告)号：US07051130B1

公开(公告)日：2006-05-23

申请号：US10882879

申请日：2004-06-30

申请人： Mark A. Horowitz ,  Richard M. Barth ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

发明人： Mark A. Horowitz ,  Richard M. Barth ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

IPC分类号： G06F13/00

CPC分类号： G06F13/4086

摘要： In an integrated circuit memory device, a transmitter circuit includes an output driver that outputs data synchronously with respect to an external clock. A register stores a value representative of a drive strength setting of the output driver. The value is determined based on information stored in a supplemental memory device.

摘要翻译： 在集成电路存储器件中，发射器电路包括输出驱动器，其相对于外部时钟同步地输出数据。 寄存器存储代表输出驱动器的驱动强度设置的值。 该值基于存储在补充存储器件中的信息来确定。

公开(公告)号：US07032058B2

公开(公告)日：2006-04-18

申请号：US11073403

申请日：2005-03-04

申请人： Mark A. Horowitz ,  Richard M. Barth ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

发明人： Mark A. Horowitz ,  Richard M. Barth ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

IPC分类号： G06F13/00

CPC分类号： G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

摘要： Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter, a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topography dependent parameter for later use by the parameter adjustment circuitry. The parameter adjustment circuitry adjusts a parameter control signal in accordance with the topography dependent parameter, which is coupled to the output driver. Prior to driving an output signal onto a bus, the output driver adjusts the transmit signal characteristic in accordance with the parameter control signal. Similarly, in a bus receiver, a receive signal characteristic is adjusted in response to a topography dependent parameter.

摘要翻译： 通过根据一个或多个地形相关参数调整信号特性来优化总线通信。 在总线发送器中，根据地形相关参数来调整发送信号特性。 总线发射器中的端口接收地形相关参数，供以后由参数调整电路使用。 参数调整电路根据与输出驱动器耦合的地形相关参数来调整参数控制信号。 在将输出信号驱动到总线之前，输出驱动器根据参数控制信号调整发送信号特性。 类似地，在总线接收器中，响应于地形相关参数来调整接收信号特性。

公开(公告)号：US06963956B2

公开(公告)日：2005-11-08

申请号：US10817781

申请日：2004-04-02

申请人： Richard M. Barth ,  Ely K. Tsern ,  Mark A. Horowitz ,  Donald C. Stark ,  Craig E. Hampel ,  Frederick A. Ware ,  Nancy David Dillon

发明人： John B. Dillon

IPC分类号： G06F13/16 ,  G11C7/10 ,  G06F12/00

CPC分类号： G11C7/1006 ,  G06F13/1615 ,  G11C7/10 ,  G11C7/1039 ,  G11C8/12 ,  G11C11/4076

摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

摘要翻译： 存储器设备具有构成流水线阶段的接口电路和存储器核心，每个阶段是与存储器核心相关联的通用序列中的步骤。 存储器件具有多个操作单元，例如预充电，感测，读取和写入，其处理操作单元耦合到的存储器核的原始操作。 存储装置还包括多个传输单元，其被配置为从外部连接获取信息，指定操作单元之一的操作并且在存储器核心和外部连接之间传送数据。 运输单元与运营单元同时运行作为流水线的附加阶段，从而创建一种在普通应用的存储器参考流下以高吞吐量和低服务时间运行的存储器件。

公开(公告)号：US06782460B2

公开(公告)日：2004-08-24

申请号：US10446880

申请日：2003-05-27

申请人： Ramprasad Satagopan ,  Richard M. Barth

发明人： Ramprasad Satagopan ,  Richard M. Barth

IPC分类号： G06F1200

CPC分类号： G06F13/1615

摘要： A memory controller for a high-performance memory system has a pipeline architecture for generating control commands which satisfy logical, timing, and physical constraints imposed on control commands by the memory system. The pipelined memory controller includes a bank state cache lookup for determining a memory bank state for a target memory bank to which a control command is addressed, and a hazard detector for determining when a memory bank does not have a proper memory bank state for receiving and processing the control command. The hazard detector stalls the operation of the control command until the memory bank is in a proper state for receiving and processing the control command. The memory controller also has a command sequencer which sequences control commands to satisfy logical constraints imposed by the memory system, and a timing coordinator to time the communication of the sequenced control commands to satisfy timing requirements imposed by the memory.

摘要翻译： 用于高性能存储器系统的存储器控​​制器具有用于产生控制命令的流水线架构，其满足由存储器系统施加在控制命令上的逻辑，定时和物理约束。 流水线存储器控制器包括用于确定用于寻址控制命令的目标存储器组的存储器组状态的存储体状态高速缓存查找器和用于确定存储器组何时不具有用于接收的适当存储器组状态的危险检测器， 处理控制命令。 危险检测器停止控制命令的操作，直到存储体处于适当的状态以接收和处理控制命令。 存储器控制器还具有命令序列器，其对控制命令进行排序以满足由存储器系统施加的逻辑约束;以及定时协调器，用于对排序的控制命令的通信进行时间以满足存储器施加的定时要求。

公开(公告)号：US06473439B1

公开(公告)日：2002-10-29

申请号：US09169372

申请日：1998-10-09

申请人： Jared LeVan Zerbe ,  Michael Tak-kei Ching ,  Abhijit M. Abhyankar ,  Richard M. Barth ,  Andy Peng-Pui Chan ,  Paul G. Davis ,  William F. Stonecypher

发明人： Jared LeVan Zerbe ,  Michael Tak-kei Ching ,  Abhijit M. Abhyankar ,  Richard M. Barth ,  Andy Peng-Pui Chan ,  Paul G. Davis ,  William F. Stonecypher

IPC分类号： H04J306

CPC分类号： G06F1/12 ,  G06F13/423 ,  H03L7/085 ,  H04L7/0012 ,  H04L7/0045 ,  H04L7/0054 ,  H04L7/02 ,  H04L7/0337

摘要： A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

摘要翻译： 公开了一种在两个同步（相同频率，不同相位）时钟域之间实现最小延迟数据传输的方法和电路。 该电路支持两个时钟域之间的任意相位关系，并且在保持相同的输出数据延迟之后容忍初始化之后的温度和电压偏移。 在一个实施例中，该电路用于总线系统以将数据从接收域，时钟重新传输到发射域时钟。 在这种系统中，这两个时钟之间的相位关系由设备总线位置设置，因此不是精确的。 通过支持任意相位重新同步，本公开允许理论上无限长的总线长度，从而不限制器件数量，以及沿着总线的器件的任意放置。 这最终允许为很长的总线支持多个延迟域。

公开(公告)号：US06373768B1

公开(公告)日：2002-04-16

申请号：US09401988

申请日：1999-09-23

申请人： Steven C. Woo ,  Ramprasad Satagopan ,  Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel

发明人： Steven C. Woo ,  Ramprasad Satagopan ,  Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel

IPC分类号： G11C704

摘要： A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory module having a plurality of memory devices coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature (actual or estimated) of the memory device. Based on the determined operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.

公开(公告)号：US06321282B1

公开(公告)日：2001-11-20

申请号：US09420949

申请日：1999-10-19

申请人： Mark A. Horowitz ,  Richard M. Barth ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

发明人： Mark A. Horowitz ,  Richard M. Barth ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

IPC分类号： G06F1300

CPC分类号： G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

摘要： Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter, a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topography dependent parameter for later use by the parameter adjustment circuitry. The parameter adjustment circuitry adjusts a parameter control signal in accordance with the topography dependent parameter, which is coupled to the output driver. Prior to driving an output signal onto a bus, the output driver adjusts the transmit signal characteristic in accordance with the parameter control signal. In a bus receiver, a receive signal characteristic is adjusted in response to a topography dependent parameter. A port associated with the bus receiver receives the topography dependent parameter and stores it in a register. Parameter adjustment circuitry adjusts a control signal in accordance with the stored topography dependent parameter. An input buffer receives an input signal from a bus coupling the receiver to a transmitter of the input signal. The input buffer generates a first signal from the input signal by adjusting a the parameter of the input signal in accordance with the control signal.

摘要翻译： 通过根据一个或多个地形相关参数调整信号特性来优化总线通信。 在总线发送器中，根据地形相关参数来调整发送信号特性。 总线发射器中的端口接收地形相关参数，供以后由参数调整电路使用。 参数调整电路根据与输出驱动器耦合的地形相关参数来调整参数控制信号。 在将输出信号驱动到总线之前，输出驱动器根据参数控制信号调整发送信号特性。 在总线接收机中，响应于地形相关参数来调整接收信号特性。 与总线接收器相关联的端口接收地形相关参数并将其存储在寄存器中。 参数调整电路根据所存储的地形相关参数调整控制信号。 输入缓冲器接收来自将接收器耦合到输入信号的发射器的总线的输入信号。 输入缓冲器根据控制信号通过调节输入信号的参数从输入信号产生第一信号。

公开(公告)号：US06310814B1

公开(公告)日：2001-10-30

申请号：US09637892

申请日：2000-08-08

申请人： Craig E. Hampel ,  Richard M. Barth ,  Paul G. Davis ,  Bradley A. May ,  Ramprasad Satagopan ,  Frederick A. Ware

发明人： Craig E. Hampel ,  Richard M. Barth ,  Paul G. Davis ,  Bradley A. May ,  Ramprasad Satagopan ,  Frederick A. Ware

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： An apparatus and method for concurrently refreshing first and second rows of memory cells in a dynamic random access memory (DRAM) component that includes a plurality of banks of memory cells organized in rows. A command interface in the DRAM component receives activate requests and precharge requests. A row register in the DRAM component indicates a row in the DRAM component. Logic in the DRAM component activates the row indicated by the row register in response to an activate request and precharges the row in response to a precharge request, the row being in a bank indicated by the activate request and by the precharge request.

摘要翻译： 一种用于在动态随机存取存储器（DRAM）组件中同时刷新第一和第二行存储器单元的装置和方法，所述动态随机存取存储器（DRAM）组件包括以行为单位组织的多组存储器单元。 DRAM组件中的命令接口接收激活请求和预充电请求。 DRAM组件中的行寄存器表示DRAM组件中的一行。 DRAM组件中的逻辑响应于激活请求而激活由行寄存器指示的行，并且响应于预充电请求预先充电该行，该行位于由激活请求指示的存储体中以及通过预充电请求。

公开(公告)号：US06266292B1

公开(公告)日：2001-07-24

申请号：US09561603

申请日：2000-04-27

申请人： Ely K. Tsern ,  Richard M. Barth ,  Paul G. Davis ,  Craig E. Hampel

发明人： Ely K. Tsern ,  Richard M. Barth ,  Paul G. Davis ,  Craig E. Hampel

IPC分类号： G11C800

CPC分类号： G11C11/40618 ,  G11C8/08 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4085 ,  G11C2211/4061 ,  G11C2211/4067

摘要： A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge currents during a refresh operation, as compared to normal memory access. Unlike normal memory accesses, data is not needed, and a fast access time is not required. This allows the current to be spread using different circuitry for driving the current to lessen current spikes. The spread current is still maintained within the timing of a normal memory access.

摘要翻译： 一种用于将通过接口总线的通信开销减少到用于刷新操作的存储器设备的方法。 这是通过刷新多个银行来响应单个命令来完成的。 与正常的存储器访问相比，通过改变在刷新操作期间的行感测和行预充电电流的电流分布，可实现多单元刷新。 与普通内存访问不同，不需要数据，不需要快速访问时间。 这允许使用不同的电路来传播电流来驱动电流以减少电流尖峰。 扩展电流仍然保持在正常内存访问的时间内。

公开(公告)号：US06178130B1

公开(公告)日：2001-01-23

申请号：US09169590

申请日：1998-10-09

申请人： Ely K. Tsern ,  Richard M. Barth ,  Paul G. Davis ,  Craig E. Hampel ,  Thomas J. Holman ,  Andrew V. Anderson

发明人： Ely K. Tsern ,  Richard M. Barth ,  Paul G. Davis ,  Craig E. Hampel ,  Thomas J. Holman ,  Andrew V. Anderson

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A memory system includes a set of memory devices. An interconnect structure links the set of memory devices to one another. A memory controller is connected to the interconnect structure. The memory controller is configured to apply a control signal to the interconnect structure such that a specified subset of the set of memory devices performs a refresh operation.

摘要翻译： 存储器系统包括一组存储器件。 互连结构将存储器件集合彼此连接。 存储器控制器连接到互连结构。 存储器控制器被配置为将控制信号施加到互连结构，使得该组存储器件的指定子集执行刷新操作。