公开(公告)号：US20240421049A1

公开(公告)日：2024-12-19

申请号：US18820361

申请日：2024-08-30

Applicant: ROHM CO., LTD.

Inventor： Takeshi OKAMOTO

IPC: H01L23/495 ,  H01L23/00 ,  H01L29/40 ,  H01L29/739

Abstract: The semiconductor device includes a semiconductor chip that has a first principal surface, a withstand-voltage holding structure in a peripheral region in the first principal surface, a plurality of first conductive layers that are formed in the first principal surface, a second conductive layer overlaps with a space between the plurality of mutually adjacent first conductive layers in a plan view, and a protective layer that covers the plurality of first conductive layers and the second conductive layer.

公开(公告)号：US20240420961A1

公开(公告)日：2024-12-19

申请号：US18439271

申请日：2024-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghoon CHOI ,  Seongsoo Kim ,  Hoyoung Kim ,  Yeongbong Park ,  Kiho Bae

IPC: H01L21/3105 ,  H01L21/3115 ,  H01L21/768 ,  H01L23/528 ,  H01L29/40

Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric film on a front-side surface of a substrate that has the front-side surface and a back-side surface, doping a surface of the first dielectric film with impurities to form a doped dielectric film covering at least a portion of the first dielectric film, forming a second dielectric film on the doped dielectric film, and polishing the second dielectric film by a chemical mechanical polishing (CMP) method. The doped dielectric film has a polishing rate less than a polishing rate of each of the first dielectric film and the second dielectric film.

公开(公告)号：US12170232B2

公开(公告)日：2024-12-17

申请号：US17647654

申请日：2022-01-11

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Fangfang Wang

IPC: H01L21/66 ,  H01L29/40 ,  H01L29/423

Abstract: The present disclosure provides a manufacturing method and measurement method of a semiconductor structure, and a semiconductor structure, relating to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a base including multiple gate trenches; and forming a gate structure in each of the gate trenches, wherein each gate structure includes a barrier layer and a conductive layer, the barrier layer and the conductive layer are sequentially stacked, the barrier layer is in contact with a bottom wall of each of the gate trenches, and a material of the conductive layers includes polysilicon.

公开(公告)号：US20240413224A1

公开(公告)日：2024-12-12

申请号：US18397293

申请日：2023-12-27

Applicant: Adeia Semiconductor Solutions LLC

Inventor： Kangguo Cheng ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L29/66 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/311 ,  H01L23/29 ,  H01L23/31 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

公开(公告)号：US12166130B2

公开(公告)日：2024-12-10

申请号：US18177202

申请日：2023-03-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jack Liu ,  Charles Chew-Yuen Young

IPC: H01L29/786 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/535 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/40

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.

公开(公告)号：US12166108B2

公开(公告)日：2024-12-10

申请号：US17747104

申请日：2022-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Yu Hung ,  Chia-Cheng Ho ,  Fei-Yun Chen ,  Yu-Chang Jong ,  Puo-Yu Chiang ,  Tun-Yi Ho

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78

Abstract: The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.

公开(公告)号：US12166070B2

公开(公告)日：2024-12-10

申请号：US17487830

申请日：2021-09-28

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Jifeng Tang

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417

Abstract: The present application discloses a semiconductor transistor structure, which includes: a substrate formed with a well region of a first conductive type, a gate structure being disposed on the substrate; a source/drain region of a second conductive type disposed in the well region of the first conductive type, the source region and the drain region being located on two sides of the gate structure respectively; a contact hole formed at a position corresponding to the source/drain region; and a conductive metal filled in the contact hole, the bottom of the contact hole being implanted with impurity ions for decreasing the contact resistance of the contact hole, and the impurity ion concentration at a peripheral region where the bottom of the contact hole comes into contact with the source/drain region being lower than the impurity ion concentration at a middle region.

公开(公告)号：US12165973B2

公开(公告)日：2024-12-10

申请号：US17344478

申请日：2021-06-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chung Chien ,  Chao-Hong Chen ,  Ming-Feng Shieh

IPC: H01L23/528 ,  H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

公开(公告)号：US20240405120A1

公开(公告)日：2024-12-05

申请号：US18329080

申请日：2023-06-05

Applicant: Infineon Technologies Austria AG

Inventor： Timothy Henson ,  Harsh Naik ,  Oliver Blank ,  Gerhard Thomas Nöbauer

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes: a plurality of transistor cells formed in a semiconductor body. The plurality of transistor cells includes: a plurality of stripe-shape gate trenches formed in a first main surface of the semiconductor body; and a plurality of field plate trenches separate from the stripe-shape gate trenches. At least one field plate trench is laterally interposed between each pair of neighboring stripe-shape gate trenches. Each stripe-shape gate trench includes a gate electrode, a gate dielectric between the gate electrode and a sidewall of the stripe-shape gate trench, and an oxide between the gate electrode and a bottom of the stripe-shape gate trench, the oxide having a vertical thickness that is greater than eight times a lateral thickness of the gate dielectric and/or greater than a vertical thickness of the gate electrode. A method of producing the semiconductor device is also described.

公开(公告)号：US20240405115A1

公开(公告)日：2024-12-05

申请号：US18671584

申请日：2024-05-22

Applicant: STMicroelectronics International N.V.

Inventor： Maria Eloisa CASTAGNA ,  Giovanni GIORGINO ,  Ferdinando IUCOLANO ,  Cristina TRINGALI ,  Aurore CONSTANT

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66

Abstract: A HEMT device including: a semiconductor body forming a heterostructure; a gate region on the semiconductor body and elongated along a first axis; a gate metal region including a lower portion on the gate region and recessed with respect to the gate region, and a upper portion on the lower portion and having a width greater that the lower portion along a second axis; a source metal region extending on the semiconductor body and made in part of aluminum; a drain metal region on the semiconductor body, the source metal region and the drain metal region on opposite sides of the gate region; a first conductivity enhancement region of aluminum nitride, extending on the semiconductor body and interposed between the source metal region and the gate region, the first conductivity enhancement region being in direct contact with the source metal region and being separated from the gate region.