公开(公告)号：US08619931B1

公开(公告)日：2013-12-31

申请号：US12622152

申请日：2009-11-19

申请人： Tien Duc Pham ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Vinh Van Ho ,  Leon Zheng

发明人： Tien Duc Pham ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Vinh Van Ho ,  Leon Zheng

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H04L7/002

摘要： Integrated circuits having transceivers capable of high-speed (e.g., 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.

摘要翻译： 提供了具有能够在没有专用锁相环电路的情况下能够进行高速（例如，1Gbps）操作的收发器的集成电路。 一个这样的集成电路设备可以包括能够发送和接收大约1Gbps或更大的串行信号的一个或多个收发器，以及能够向一个或多个收发器提供多相时钟信号的多用途锁相环。

公开(公告)号：US08571159B1

公开(公告)日：2013-10-29

申请号：US13310513

申请日：2011-12-02

申请人： Lip Kai Soh

发明人： Lip Kai Soh

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/093 ,  H04L7/0008 ,  H04L7/002 ,  H04L7/0025 ,  H04L7/0331

摘要： One embodiment relates to an interpolator-based clock and data recovery circuit which includes a de-multiplexer and a voting circuit. The de-multiplexer is arranged to de-multiplex a feedback signal from a sampler, and the voting circuit is arranged decimate the de-multiplexed feedback signal. The decimated feedback signal may be provided to a digital filter. Another embodiment relates to a method for clock and data recovery from a data signal. The method includes de-multiplexing and decimation of a feedback signal. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及一种基于插值器的时钟和数据恢复电路，其包括解复用器和投票电路。 解复用器被布置为对来自采样器的反馈信号进行解复用，并且投票电路被布置为对去多路复用的反馈信号进行抽取。 抽取的反馈信号可以被提供给数字滤波器。 另一实施例涉及一种用于从数据信号进行时钟和数据恢复的方法。 该方法包括解复用和抽取反馈信号。 还公开了其它实施例和特征。

公开(公告)号：US20130188749A1

公开(公告)日：2013-07-25

申请号：US13612796

申请日：2012-09-12

申请人： Chi-Hsueh Wang ,  Kai-Peng Kao ,  Robert Bogdan Staszewski

发明人： Chi-Hsueh Wang ,  Kai-Peng Kao ,  Robert Bogdan Staszewski

IPC分类号： H04L25/02

CPC分类号： H03C5/00 ,  H04L7/002 ,  H04L7/0331

摘要： A polar transmitter includes a frequency modulating path, a clock divider and a digital processing block. The frequency modulating path is arranged for generating a frequency modulated clock in response to a frequency modulating signal. The clock divider is coupled to the frequency modulated clock, and arranged for generating a down-divided clock. The digital processing block is coupled to the down-divided clock, and arranged for generating the frequency modulating signal, wherein the frequency modulating signal is adjusted for frequency deviation of the frequency modulated clock. A method for polar transmission includes: generating a frequency modulated clock in response to a frequency modulating signal; dividing a frequency of said frequency modulated clock to generate a down-divided clock; and generating said frequency modulating signal according to said down-divided clock, wherein said frequency modulating signal is adjusted for frequency deviation of said frequency modulated clock.

摘要翻译： 极性发射机包括频率调制路径，时钟分频器和数字处理模块。 频率调制路径被布置成响应于频率调制信号而产生调频时钟。 时钟分频器耦合到频率调制时钟，并且被布置用于产生分频时钟。 数字处理块耦合到分频时钟，并且被配置为产生频率调制信号，其中调频信号针对频率调制时钟的频率偏差。 一种用于极性传输的方法包括：响应于频率调制信号产生调频时钟; 将所述调频时钟的频率除以产生下降时钟; 以及根据所述分频时钟产生所述频率调制信号，其中调节所述频率调制信号以调节所述频率调制时钟的频率偏差。

公开(公告)号：US20120281140A1

公开(公告)日：2012-11-08

申请号：US13465971

申请日：2012-05-07

申请人： Raul Alejandro Casas ,  Stephen Biracree ,  Anand Mahendra Shah ,  Slobodan Simovich ,  Thomas Joseph Endres

发明人： Raul Alejandro Casas ,  Stephen Biracree ,  Anand Mahendra Shah ,  Slobodan Simovich ,  Thomas Joseph Endres

IPC分类号： H04N5/04

CPC分类号： H04N21/42676 ,  H04L7/002 ,  H04L7/0041 ,  H04L25/0202 ,  H04L25/03006 ,  H04L2027/0053 ,  H04L2027/0073

摘要： The current application is directed to maintaining the correct number of symbols in a protocol frame in a digital communications receiver, to prevent catastrophic failure due to dynamic multipath or cycle slips. Timing recovery and framing are coherent, facilitated by placing channel estimation directly into a larger timing recovery loop.

摘要翻译： 当前的应用涉及在数字通信接收机中的协议帧中维持正确数量的符号，以防止由于动态多径或周期滑移导致的灾难性故障。 通过将信道估计直接放置在更大的定时恢复循环中，定时恢复和帧定时是一致的。

公开(公告)号：US08063686B1

公开(公告)日：2011-11-22

申请号：US12270038

申请日：2008-11-13

申请人： Eric Naviasky ,  Thomas E. Wilson

发明人： Eric Naviasky ,  Thomas E. Wilson

IPC分类号： H03H11/16 ,  H03K5/13

CPC分类号： H03K5/135 ,  H03K2005/00052 ,  H04L7/002 ,  H04L7/0337

摘要： In one embodiment of the invention, a method is disclosed to generate a clock output signal with selected phase. The method includes selecting a phase delay for the clock output signal; charging a capacitor with a first weighted current during a first phase input clock, charging the capacitor with a second weighted current during a portion of a second phase input clock, and determining if a voltage across the capacitor is greater than or equal to a threshold voltage to generate a first edge of the clock output signal with the selected phase delay. The first weighted current may have a weighting of N out of M to charge the capacitor with a predetermined rate of change in voltage in response to the selected phase delay. The second weighted current may have a weighting of M out of M to charge the capacitor with a constant rate of change.

摘要翻译： 在本发明的一个实施例中，公开了一种用于产生具有所选相位的时钟输出信号的方法。 该方法包括选择时钟输出信号的相位延迟; 在第一相位输入时钟期间用第一加权电流对电容器充电，在第二相输入时钟的一部分期间用第二加权电流对电容器充电，以及确定电容器两端的电压是否大于或等于阈值电压 以产生具有所选相位延迟的时钟输出信号的第一边沿。 第一加权电流可以具有对M的加权，以响应于所选择的相位延迟以预定的电压变化率对电容器充电。 第二加权电流可以具有M的M的加权，以恒定的变化率对电容器充电。

公开(公告)号：US20100209121A1

公开(公告)日：2010-08-19

申请号：US12707113

申请日：2010-02-17

申请人： Takahito TANIMURA

发明人： Takahito TANIMURA

IPC分类号： H04B10/06 ,  G02F1/01

CPC分类号： H04B10/611 ,  H04B10/613 ,  H04B10/6162 ,  H04J14/06 ,  H04L7/002 ,  H04L7/0335

摘要： A signal processing device includes: a phase controller configured to control respective phases of an in-phase signal and an quadrature signal, which are obtained by converting an analog signal into a digital signal when a multi-value phase modulation light is demodulated, by digital signal processing; and a control amount provider configured to provide a control amount to the phase controller based on an output of the phase controller.

摘要翻译： 一种信号处理装置，包括：相位控制器，被配置为控制同相信号和正交信号的各个相位，所述相位相位和正交信号是通过数字地将多值相位调制光解调时将模拟信号转换为数字信号而获得的 信号处理; 以及控制量提供器，被配置为基于所述相位控制器的输出向所述相位控制器提供控制量。

公开(公告)号：US20180304011A1

公开(公告)日：2018-10-25

申请号：US16020961

申请日：2018-06-27

申请人： Abbott Diabetes Care Inc.

发明人： Mark Kent Sloan

IPC分类号： A61M5/172 ,  A61B5/00 ,  H04L7/00

CPC分类号： A61M5/1723 ,  A61B5/0002 ,  A61B5/01 ,  A61B5/14532 ,  A61M2205/3592 ,  G06F19/3418 ,  G16H40/63 ,  G16H40/67 ,  H04B7/24 ,  H04L7/002 ,  H04L7/0079 ,  H04L7/0091

摘要： Method and system for providing data monitoring and management including RF communication link over which a transmitter and a receiver is configured to communicate, the transmitter configured to periodically transmit a data packet associated with a detected analyte level received from an analyte sensor, and the receiver configured to identify the transmitter as the correct transmitter for which it is configured to receive the data packets, and to continue to receive the data packets from the transmitter once the transmitter identification has been verified, is provided.

公开(公告)号：US09780797B2

公开(公告)日：2017-10-03

申请号：US15464750

申请日：2017-03-21

申请人： INPHI CORPORATION

发明人： Karthik S. Gopalakrishnan ,  Guojun Ren ,  Parmanand Mishra

IPC分类号： H03L7/081 ,  H03L7/08 ,  H04L25/03

CPC分类号： H03L7/0812 ,  H03K5/131 ,  H03K5/135 ,  H03K5/14 ,  H03K2005/00013 ,  H03K2005/00052 ,  H03K2005/00286 ,  H03L3/00 ,  H03L7/08 ,  H03L7/0807 ,  H03L7/0814 ,  H04L5/0053 ,  H04L7/002 ,  H04L7/0331 ,  H04L25/03273 ,  H04L27/04

摘要： The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer (SerDes) device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications. In various embodiments, phase-interpolator is implemented in conjunction with a delay-lock loop (DLL) and an SR latch, where one or more outputs of the DLL is used by the SR latch. Additionally, such techniques can be used for a variety of applications such as network and/or computer storage systems, computer servers, hand held computing devices, portable computing devices, computer systems, network appliances and/or switches, routers, and gateways, and the like.

公开(公告)号：US09692587B2

公开(公告)日：2017-06-27

申请号：US14922345

申请日：2015-10-26

申请人： Higher Ground LLC

发明人： Bruce L. McKinley

IPC分类号： H04L7/00 ,  H04L27/26

CPC分类号： H04L7/002 ,  H04B1/7087 ,  H04L7/0079 ,  H04L27/0014 ,  H04L27/2605 ,  H04L27/2613 ,  H04L27/2657 ,  H04L27/2662 ,  H04L27/2675 ,  H04L2027/0067

摘要： Techniques for pilot-aided carrier frequency and phase synchronization may use a three-pass process. In a first pass, initial frequency offset may be addressed, and a frame start time may be established. In a second pass, a fine frequency correction may be performed. In a third pass, phase variation may be tracked and corrected using a minimum set of pilot symbols.

公开(公告)号：US09577815B1

公开(公告)日：2017-02-21

申请号：US14926958

申请日：2015-10-29

申请人： Kandou Labs, S.A.

发明人： Richard Simpson ,  Andrew Kevin John Stewart ,  Ali Hormati

IPC分类号： H04L7/00

CPC分类号： H04L7/0012 ,  H04L7/002 ,  H04L7/0025 ,  H04L7/0337 ,  H04L25/14 ,  H04L25/49

摘要： A communications system receiver is described providing automatic timing adjustment of receive data sampling. A concurrently received clock signal is used as both a reference for generation of internal receiver timing signals, and as an exemplar for adjustment of those timing signals to optimize received data sample timing.

摘要翻译： 描述了提供接收数据采样的自动定时调整的通信系统接收机。 同时接收的时钟信号用作产生内部接收机定时信号的参考，并且作为用于调整那些定时信号以优化接收数据采样定时的示例。