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1.发明申请HETEROGENEOUS PHYSICAL MEDIA ATTACHMENT CIRCUITRY FOR INTEGRATED CIRCUIT DEVICES 有权用于集成电路设备的异质物理介质连接电路公开(公告)号：US20110285434A1
公开(公告)日：2011-11-24
申请号：US12785047
申请日：2010-05-21
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , H03K19/1774 , H03K19/17744 , H03L7/0891 , H03L7/095
摘要： An integrated circuit includes physical media attachment (“PMA”) circuitry that includes two different kinds of transceiver channels for serial data signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively usable as phase-locked loop (“PLL”) circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.
摘要翻译： 集成电路包括物理介质连接（“PMA”）电路，其包括用于串行数据信号的两种不同类型的收发信道。 一种收发信道用于收发相对低速的串行数据信号。 另一种收发器通道适用于收发相对高速的串行数据信号。 高速通道可用作锁相环（“PLL”）电路，用于提供其它高速和/或低速通道使用的时钟信号。 低速通道也可以从单独的低速PLL电路获取时钟信号。
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公开(公告)号：US08664983B1
公开(公告)日：2014-03-04
申请号：US13427298
申请日：2012-03-22
申请人： Lip Kai Soh
发明人： Lip Kai Soh
IPC分类号： H03L7/00
摘要： A clock data recovery circuit includes a sampler circuit, a filter circuit, a control circuit, and a phase shift circuit. The sampler circuit samples input data in response to a clock signal. The filter circuit is coupled to the sampler circuit. The control circuit is coupled to the filter circuit. The phase shift circuit provides the clock signal to the sampler circuit. The control circuit causes the phase shift circuit to shift a phase of the clock signal by a first phase shift, and by a second phase shift after the phase of the clock signal has shifted by the first phase shift, in response to the filter circuit indicating to shift the phase of the clock signal by more than a predefined phase shift.
摘要翻译： 时钟数据恢复电路包括采样电路，滤波电路，控制电路和相移电路。 采样器电路响应于时钟信号采样输入数据。 滤波器电路耦合到采样器电路。 控制电路耦合到滤波电路。 相移电路向采样电路提供时钟信号。 控制电路使得相移电路将时钟信号的相位移位第一相移，并且在时钟信号的相位偏移第一相移之后，响应于滤波器电路指示 以使时钟信号的相位偏移大于预定义的相移。
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3.发明授权Apparatus and methods for lock detection for semi-digital and fully-digital clock data recovery 有权用于半数字和全数字时钟数据恢复的锁定检测的装置和方法公开(公告)号：US08610476B1
公开(公告)日：2013-12-17
申请号：US13618832
申请日：2012-09-14
申请人： Lip Kai Soh
发明人： Lip Kai Soh
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , H03L7/0807 , H03L7/0814 , H03L7/091
摘要： One embodiment relates to a lock detection circuit. The lock detection circuit includes at least a dither detection circuit and a lock filter. The dither detection circuit maintains a bi-directional count based on early and late signals from a sampler circuit and asserts a non-lock signal if the bi-directional count reaches either a positive non-lock assertion threshold or a negative non-lock assertion threshold. The lock filter increments a lock filter count for each sample and outputs a lock-initiated signal when the lock filter count reaches a pre-set maximum value. The maximum value of the lock filter count is greater than the non-lock assertion thresholds. Other embodiments and features are also disclosed.
摘要翻译： 一个实施例涉及锁定检测电路。 锁定检测电路至少包括抖动检测电路和锁定滤波器。 抖动检测电路基于来自采样器电路的早期和晚期信号保持双向计数，并且如果双向计数达到正非锁定断言阈值或负非锁定断言阈值，则确定非锁定信号 。 锁定过滤器对每个样品增加锁定过滤器计数，并在锁定过滤器计数达到预设最大值时输出锁定起始信号。 锁定过滤器计数的最大值大于非锁定断言阈值。 还公开了其它实施例和特征。
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公开(公告)号：US07839177B1
公开(公告)日：2010-11-23
申请号：US12266935
申请日：2008-11-07
申请人： Lip Kai Soh
发明人： Lip Kai Soh
CPC分类号： H03D13/00
摘要： A phase detector includes transistors that generate first and second phase error signals. The phase detector resets the first phase error signal in response to at least one of the first and the second phase error signals through a first reset path having a maximum reset delay that is equal to or less than a sum of switching delays of three transistors in the first reset path. The phase detector resets the second phase error signal in response to at least one of the first and the second phase error signals through a second reset path having a maximum reset delay that is equal to or less than a sum of switching delays of three transistors in the second reset path.
摘要翻译： 相位检测器包括产生第一和第二相位误差信号的晶体管。 相位检测器响应于第一和第二相位误差信号中的至少一个通过具有等于或小于三个晶体管的切换延迟之和的第一复位延迟来复位第一相位误差信号 第一个复位路径。 相位检测器响应于第一和第二相位误差信号中的至少一个通过具有等于或小于三个晶体管的切换延迟之和的第二复位路径复位第二相位误差信号 第二个复位路径。
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5.发明授权Apparatus and methods for high-speed interpolator-based clock and data recovery 有权用于基于高速内插器的时钟和数据恢复的装置和方法公开(公告)号：US08571159B1
公开(公告)日：2013-10-29
申请号：US13310513
申请日：2011-12-02
申请人： Lip Kai Soh
发明人： Lip Kai Soh
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/002 , H04L7/0025 , H04L7/0331
摘要： One embodiment relates to an interpolator-based clock and data recovery circuit which includes a de-multiplexer and a voting circuit. The de-multiplexer is arranged to de-multiplex a feedback signal from a sampler, and the voting circuit is arranged decimate the de-multiplexed feedback signal. The decimated feedback signal may be provided to a digital filter. Another embodiment relates to a method for clock and data recovery from a data signal. The method includes de-multiplexing and decimation of a feedback signal. Other embodiments and features are also disclosed.
摘要翻译： 一个实施例涉及一种基于插值器的时钟和数据恢复电路，其包括解复用器和投票电路。 解复用器被布置为对来自采样器的反馈信号进行解复用，并且投票电路被布置为对去多路复用的反馈信号进行抽取。 抽取的反馈信号可以被提供给数字滤波器。 另一实施例涉及一种用于从数据信号进行时钟和数据恢复的方法。 该方法包括解复用和抽取反馈信号。 还公开了其它实施例和特征。
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6.发明授权Heterogeneous physical media attachment circuitry for integrated circuit devices 有权用于集成电路器件的异质物理介质连接电路公开(公告)号：US08397096B2
公开(公告)日：2013-03-12
申请号：US12785047
申请日：2010-05-21
CPC分类号： H03L7/0805 , H03K19/1774 , H03K19/17744 , H03L7/0891 , H03L7/095
摘要： An integrated circuit includes physical media attachment (“PMA”) circuitry that includes two different kinds of transceiver channels for serial data signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively usable as phase-locked loop (“PLL”) circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.
摘要翻译： 集成电路包括物理介质连接（PMA）电路，其包括用于串行数据信号的两种不同类型的收发信道。 一种收发信道用于收发相对低速的串行数据信号。 另一种收发器通道适用于收发相对高速的串行数据信号。 高速通道可用作锁相环（PLL）电路，用于提供时钟信号以供其他高速和/或低速通道使用。 低速通道也可以从单独的低速PLL电路获取时钟信号。
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公开(公告)号：US08350596B1
公开(公告)日：2013-01-08
申请号：US12748320
申请日：2010-03-26
申请人： Lip Kai Soh
发明人： Lip Kai Soh
IPC分类号： H03K5/19
CPC分类号： H03K5/1534 , H03K19/00346 , H03L2207/14
摘要： A clock loss detection circuit is presented. The clock loss detection has two edge detection circuits and a clock loss detect counter circuit. Each edge detection circuit includes a reset signal circuit that generates a reset signal in response to a transition of a clock signal, and the reset signal circuit is connected to a clock input of the edge detection circuit. Each edge detection circuit also has a multiplexer connected to the reset signal circuit, and another multiplexer connected to the clock input. The clock loss detect counter circuit is connected to the edge detection circuits so that the clock loss detect counter circuit receives the reset signal from the second edge detection circuit and the clock signal from the first edge detection circuit.
摘要翻译： 提出了一种时钟损耗检测电路。 时钟损耗检测具有两个边沿检测电路和一个时钟损耗检测计数器电路。 每个边缘检测电路包括响应于时钟信号的转变而产生复位信号的复位信号电路，并且复位信号电路连接到边缘检测电路的时钟输入端。 每个边缘检测电路还具有连接到复位信号电路的多路复用器，另一个多路复用器连接到时钟输入。 时钟损耗检测计数器电路连接到边缘检测电路，使得时钟损耗检测计数器电路接收来自第二边缘检测电路的复位信号和来自第一边缘检测电路的时钟信号。
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