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    EXPANSION OF ALLOWED DESIGN RULE SPACE BY WAIVING BENIGN GEOMETRIES
    41.
    发明申请
    EXPANSION OF ALLOWED DESIGN RULE SPACE BY WAIVING BENIGN GEOMETRIES 审中-公开

    公开(公告)号：US20180096093A1

    公开(公告)日：2018-04-05

    申请号：US15281183

    申请日：2016-09-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ioana C. Graur ,  Dmitry Vengertsev

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/12

    Abstract: Systems, methods, and computer program products for design rules checking in which the waiver of design rules is optimized while ensuring compliant designs that are manufacturable. A first design rule and a plurality of patterns of a layout that violate the first design rule are received by a design rule waiver system. The design rule waiver system may process the first design rule to extract a plurality of descriptors that can be perturbed. The design rule waiver system may perturb an attribute associated with at least one of the plurality of descriptors extracted from the first design rule in order to define a second design rule that is satisfied by the plurality of patterns.

    EMBEDDED SECURITY ELEMENTS FOR DIGITAL MODELS USED IN ADDITIVE MANUFACTURING
    44.
    发明申请
    EMBEDDED SECURITY ELEMENTS FOR DIGITAL MODELS USED IN ADDITIVE MANUFACTURING 审中-公开

    公开(公告)号：US20180081997A1

    公开(公告)日：2018-03-22

    申请号：US15710723

    申请日：2017-09-20

    Applicant: NEW YORK UNIVERSITY

    Inventor： Nikhil GUPTA

    IPC: G06F17/50 ,  B29C64/386 ,  B33Y50/00

    CPC classification number: G06F17/50 ,  B29C64/386 ,  B33Y50/00 ,  B33Y80/00 ,  G06F2217/12 ,  H04N1/00838 ,  Y02P90/265

    Abstract: A method for securing a computer-aided design (CAD)-based shape to prevent shape counterfeiting by unauthorized three-dimensional (3D) printing includes creating and embedding a security element in the CAD-based shape itself. In some embodiments, the method includes splitting (slicing) a first solid of a three-dimensional 3D model into at least two parts, such that the 3D model comprises at least two distinct solids. The shape of the distinct solid(s) may be specified by a plurality of curved surfaces, which are defined by performing a finite element analysis on the CAD-based shape to determine an optimal shape for each curved surface. The method further includes converting the 3D model to a digital surface geometry schema according to a first resolution. The digital surface geometry schema describes the surface geometry of the at least two distinct solids. The first resolution is part of the security controls of the CAD-based shape. The first resolution may be selected based on a shape of the split of the first solid, a location of the split of the first solid, a 3D printer type, an anticipated horizontal print direction, an anticipated vertical print direction, an anticipated slicer software scheme, an anticipated slice thickness, and/or an anticipated slice location.

    Negative plane usage with a virtual hierarchical layer
    45.
    发明授权
    Negative plane usage with a virtual hierarchical layer 有权

    公开(公告)号：US09916411B2

    公开(公告)日：2018-03-13

    申请号：US14713488

    申请日：2015-05-15

    Applicant: Synopsys, Inc.

    Inventor： Gary B Nifong ,  Jun Chen ,  Karthikeyan Muthalagu ,  James Lewis Nance

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/50 ,  G06F17/5009 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A virtual hierarchical layer (VHL) is constructed for a semiconductor design in order to reduce the computational requirement of design rules checking (DRC) and design rules for manufacture (DRM) procedures. In order to form the VHL, a negative plane is created. A cell and multiple instances of the cell are then identified in the semiconductor design and polygons which overlap the cell and its instances are determined. The polygons are pushed into the negative plane to create holes in the plane. Shapes overlapping other instances of the cell which fall onto holes in the solid virtual cell plane are ignored. The resulting holed solid virtual cell plane can then be inverted to create a VHL to be used for design simulation and verification.

    INTEGRATED CIRCUIT DESIGN LAYOUT OPTIMIZER BASED ON PROCESS VARIATION AND FAILURE MECHANISM
    48.
    发明申请
    INTEGRATED CIRCUIT DESIGN LAYOUT OPTIMIZER BASED ON PROCESS VARIATION AND FAILURE MECHANISM 审中-公开

    公开(公告)号：US20180046746A1

    公开(公告)日：2018-02-15

    申请号：US15235273

    申请日：2016-08-12

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Lawrence A. Clevenger ,  Jason D. Hibbeler ,  Dongbing Shao ,  Robert C. Wong

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/12 ,  H01L2924/37001

    Abstract: Embodiments include methods, design layout optimization systems, and computer program products for optimizing design layout of integrated circuits. Aspects include receiving a design layout of an integrated circuit from a design layout tool module, identifying a critical pitch in the design layout received, searching design rules forming design arc limited by identified critical pitch from a set of design rules associated with the received design layout, extracting a process variation and one or more failure mechanisms of design layout based on critical pitch and rules forming design arc identified, performing layout based ground rule calculation based on the process variation and the one or more failure mechanisms extracted, determining whether wafer risks exist in the design layout, responsive to determining the wafer risks exist in the design layout, revising the design layout and performing additional layout based ground rule calculation after the revision, and otherwise, outputting an optimized design layout.

    SYSTEMS AND METHODS FOR CELL ABUTMENT
    49.
    发明申请
    SYSTEMS AND METHODS FOR CELL ABUTMENT 审中-公开

    公开(公告)号：US20180046744A1

    公开(公告)日：2018-02-15

    申请号：US15334918

    申请日：2016-10-26

    Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

    Inventor： Wan-Ru Lin ,  Ching-Shun Yang

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    Abstract: The present disclosure is directed to systems and methods for cell placement. In embodiments, the methods include placing a plurality of cells selected from a cell library in a chip design to produce a first cell placement and determining whether the first cell placement satisfies design demands. In further embodiments, the method also includes rearranging a first cell to abut the first cell with a second cell when the first cell placement fails to satisfy design demands. In still further embodiments, the first cell is rearranged until a second cell placement providing a minimum metal route between the first and second cells is determined. In various embodiments, the method further includes generating a design layout based on the second cell placement and outputting the design layout to a machine readable storage medium. The outputted layout is used to manufacture a set of masks used in chip fabrication processes.

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