公开(公告)号：US4435763A

公开(公告)日：1984-03-06

申请号：US253957

申请日：1981-04-13

申请人： Jeffrey D. Bellay ,  Robert C. Thaden ,  John W. Hayn ,  Kevin C. McDonough

发明人： Jeffrey D. Bellay ,  Robert C. Thaden ,  John W. Hayn ,  Kevin C. McDonough

IPC分类号： G06F1/22 ,  G06F3/00

CPC分类号： G06F1/22

摘要： A electronic digital processor system input/output circuitry including several input/output data ports where each port contains receiving circuitry to receive bit data from bit data pads and transmitting circuitry to transmit bit data to the data bit pads and control circuitry that provides for a configuration where one input/output port may respond to the address of another input/output port, allowing the second input/output port to perform other functions. This capability would allow a user to execute a program that emulates one configuration while the actual, physical connection of devices is, in fact, another configurations. The input/output circuitry also include control circuitry that determines whether the port is to receive bit data or to transmit bit data. This circuitry is connected to a data bus that couples the input/output data ports to the remaining electronic digital processor system.

摘要翻译： 一种电子数字处理器系统输入/输出电路，其包括多个输入/输出数据端口，其中每个端口包含接收电路以从位数据焊盘接收位数据，并且传输电路将位数据发送到提供配置的数据位焊盘和控制电路 其中一个输入/输出端口可以响应另一个输入/输出端口的地址，允许第二个输入/输出端口执行其他功能。 该功能将允许用户执行仿真一个配置的程序，而设备的实际物理连接实际上是另一种配置。 输入/输出电路还包括控制电路，其确定端口是接收位数据还是发送位数据。 该电路连接到将输入/输出数据端口耦合到剩余电子数字处理器系统的数据总线。

公开(公告)号：US4330842A

公开(公告)日：1982-05-18

申请号：US939723

申请日：1978-09-05

申请人： R. Gary Daniels ,  Thomas H. Bennett ,  Michael F. Wiles

发明人： R. Gary Daniels ,  Thomas H. Bennett ,  Michael F. Wiles

IPC分类号： G06F1/22 ,  G06F13/42 ,  G06F3/00 ,  G06F13/00

CPC分类号： G06F1/22 ,  G06F13/4243

摘要： A digital data processor on a single monolithic integrated circuit chip is provided which uses one less pin. The elimination of the pin is accomplished by using, internally to the processor, a valid memory address signal to gate information from the address but to an address output line. Whenever an address is not present on the address bus all logic "1's" are generated on the address output bus.

摘要翻译： 提供了单个单片集成电路芯片上的数字数据处理器，其使用少一个引脚。 通过在处理器内部使用有效的存储器地址信号到从地址到地址输出线的门信息来实现引脚的消除。 每当地址总线上不存在地址时，地址输出总线上都会产生逻辑“1”。

公开(公告)号：US3879713A

公开(公告)日：1975-04-22

申请号：US40713273

申请日：1973-10-17

申请人： OLYMPIA WERKE AG

发明人： BETTIN HUBERTUS ,  FOLTA ALFRED

IPC分类号： G06F3/00 ,  G06F1/22 ,  G06F3/02 ,  G06F3/023 ,  G06F3/0489 ,  H03M11/20 ,  G06F3/12

CPC分类号： H03M11/20 ,  G06F1/22 ,  G06F3/0227 ,  G06F3/0489

摘要： A circuit arrangement for transmitting signals between a data processing unit and external input and output units. The data processing unit has a plurality of terminals. A plurality of first switching circuits are provided, each being connected to a respective one of the terminals. These first switching circuits, in their normal position, connect the terminals to the output unit. A control circuit is connected to the input unit and provides control signals in response to a determination that information to be supplied to the data processing unit is present at the input unit. The control circuit in response to such a determination causes the switching circuits to temporarily switch so as to connect the input unit to the data processing unit.

摘要翻译： 一种用于在数据处理单元和外部输入和输出单元之间传送信号的电路装置。 数据处理单元具有多个终端。 提供多个第一开关电路，每个都连接到相应的一个端子。 这些第一开关电路在其正常位置将端子连接到输出单元。 控制电路连接到输入单元，并响应于要提供给数据处理单元的信息存在于输入单元的确定而提供控制信号。 响应于这种确定的控制电路使得切换电路暂时切换，以将输入单元连接到数据处理单元。

公开(公告)号：US11899655B2

公开(公告)日：2024-02-13

申请号：US17397124

申请日：2021-08-09

申请人： Walmart Apollo, LLC

发明人： Sandeep Malik ,  Chintan Pankajkumar Shah

IPC分类号： G06F16/23 ,  G06F16/22 ,  G06F9/54 ,  G06F1/22

CPC分类号： G06F16/2379 ,  G06F1/22 ,  G06F9/542 ,  G06F9/546

摘要： Systems and methods including one or more processors and one or more non-transitory media storing computing instructions that, when executed on the one or more processors, cause the one or more processors to perform: storing one or more notifications in a data store; receiving a new notification; determining a respective number of notifications in each respective segment of a plurality of approximately equal segments; using the respective number of notifications in each respective segment of the plurality of approximately equal segments to determine a number of the one or more notifications; when the number of the one or more notifications is equal to or greater than a maximum number of notifications, removing at least one notification of the one or more notifications; and before or after removing the at least one notification, storing the new notification in the data store.

公开(公告)号：US20190244880A1

公开(公告)日：2019-08-08

申请号：US16266727

申请日：2019-02-04

申请人： Johnson Electric International AG

发明人： Chiping SUN ,  Shinghin YEUNG ,  Haibo JIANG ,  Qiubao WANG ,  Enhui WANG

IPC分类号： H01L23/495 ,  H01L23/50 ,  H01L23/00

CPC分类号： H03K19/1732 ,  G06F1/22

摘要： An IC includes a bare die and a multiplexed pin. The multiplexed pin is electrically connected to first and second switch circuits, the first and second switch circuits are respectively connected to first and second circuit modules disposed on the bare die and control a connection between the first and second circuit modules and the multiplexed pin, the first switch circuit is connected to a first die pad by a metal layer trace within the bare die, the second switch circuit is connected to a second die pad by a metal layer trace within the bare die, and the first and second die pads are connected to the multiplexed pin through a bond wire respectively. The bare die with a larger number of die pads can be packaged into an IC package with a smaller number of chip pins.

公开(公告)号：US20160266631A1

公开(公告)日：2016-09-15

申请号：US15041979

申请日：2016-02-11

申请人： Skyworks Solutions, Inc.

发明人： Kevin P. d'Angelo ,  David Alan Brown ,  John Sung K. So ,  Jan Nilsson ,  Richard K. Williams

IPC分类号： G06F1/28 ,  G06F9/44 ,  G06F1/12

CPC分类号： G06F1/28 ,  G06F1/04 ,  G06F1/06 ,  G06F1/12 ,  G06F1/22 ,  G06F9/4403 ,  G06F13/4291 ,  G09G3/3406 ,  G09G5/10 ,  G09G2320/0233 ,  H05B33/0803 ,  H05B33/0815 ,  H05B33/0851

摘要： A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.

公开(公告)号：US20150356039A1

公开(公告)日：2015-12-10

申请号：US14729402

申请日：2015-06-03

申请人： MICROCHIP TECHNOLOGY INCORPORATED

发明人： Bryan Kris

IPC分类号： G06F13/38 ,  G06F13/28

CPC分类号： G06F13/385 ,  G06F1/22 ,  G06F13/287 ,  G06F15/76

摘要： An embedded device has a plurality of processor cores, each with a plurality of peripheral devices, wherein each peripheral device may have an output, a housing with a plurality of assignable external pins, and a plurality of peripheral pin selection modules for each processing core, wherein each peripheral pin selection module is configured to be programmable to assign an assignable external pin to one of the plurality of peripheral devices of one of the processor cores.

摘要翻译： 嵌入式设备具有多个处理器核心，每个处理器核心具有多个外围设备，其中每个外围设备可以具有输出，具有多个可分配的外部引脚的外壳以及用于每个处理核心的多个外围引脚选择模块， 其中每个外围引脚选择模块被配置为可编程以将可分配的外部引脚分配给所述处理器核心之一的所述多个外围设备之一。

公开(公告)号：US20150254208A1

公开(公告)日：2015-09-10

申请号：US14722299

申请日：2015-05-27

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Yu-Lan Kuo ,  Chun-Hsiung Hung

IPC分类号： G06F13/42 ,  G06F13/40

CPC分类号： G06F13/4291 ,  G06F1/22 ,  G06F13/385 ,  G06F13/40 ,  G06F13/4022 ,  G06F13/404

摘要： A serial peripheral interface of an integrated circuit includes: a first transfer pin for receiving an instruction and an address; and a clock pin for inputting a plurality of timing pulses each having a rising edge and a falling edge. After the first transfer pin receives the instruction, the integrated circuit receives the address through the first transfer pin in continuity with the receipt of the instruction. The first transfer pin receives the instruction at either of the rising edges and the falling edges of the timing pulses and receives the address at both of the rising edges and falling edges of the timing pulses.

摘要翻译： 集成电路的串行外围接口包括：用于接收指令和地址的第一传输引脚; 以及用于输入多个具有上升沿和下降沿的定时脉冲的时钟引脚。 在第一个传输引脚接收到指令之后，集成电路通过第一个传输引脚连续接收指令。 第一传输引脚在定时脉冲的上升沿和下降沿中的任一个接收指令，并在定时脉冲的两个上升沿和下降沿接收地址。

公开(公告)号：US09104213B2

公开(公告)日：2015-08-11

申请号：US13798147

申请日：2013-03-13

申请人： uPI Semiconductor Corp.

发明人： Hung-Hsuan Cheng ,  Wei-Ling Chen

IPC分类号： G05F3/02 ,  G06F1/22

CPC分类号： G05F3/02 ,  G06F1/22

摘要： An integrated circuit with multi-functional parameter setting and a multi-functional parameter setting method thereof are provided. The multi-functional parameter setting method includes the following steps: providing the integrated circuit, wherein the integrated circuit includes a multi-functional pin and a switch unit, wherein the multi-functional pin is coupled to an external setting unit, and the switch unit includes an operational amplifier; sensing a programmable reference voltage of the external setting unit through one operation of the switch unit and executing a first function setting according to the programmable reference voltage; and sensing a programmable reference current related to the external setting unit through another operation of the switch unit and executing a second function setting according to the programmable reference current, wherein a value of the programmable reference current is related to the programmable reference voltage.

摘要翻译： 提供具有多功能参数设定的集成电路及其多功能参数设定方法。 多功能参数设定方法包括以下步骤：提供集成电路，其中所述集成电路包括多功能引脚和开关单元，其中所述多功能引脚耦合到外部设置单元，并且所述开关单元 包括运算放大器; 通过开关单元的一个操作来感测外部设置单元的可编程参考电压，并根据可编程参考电压执行第一功能设置; 以及通过所述开关单元的另一操作来感测与所述外部设置单元相关的可编程参考电流，并且根据所述可编程参考电流执行第二功能设置，其中所述可编程参考电流的值与所述可编程参考电压相关。

公开(公告)号：US08880746B2

公开(公告)日：2014-11-04

申请号：US11343984

申请日：2006-01-31

申请人： Kenneth M. Rose ,  David S. Walker

发明人： Kenneth M. Rose ,  David S. Walker

IPC分类号： G06F3/00 ,  G06F1/22 ,  G06F9/445

CPC分类号： G06F1/22 ,  G06F9/44505

摘要： An apparatus and method for unconditionally loading a value into first memory of an first integrated circuit, which operates in one of several different modes depending on value stored in the first memory. In one embodiment, apparatus comprises a printed circuit board. The first integrated circuit (IC) is mounted on the printed circuit board, wherein the first IC comprises a first memory device, and wherein the first IC is configured to operate in a first mode when a first value is stored in the first memory device, and wherein the first IC is configured to operate in a second mode when a second value is stored in the first memory device. The printed circuit board also includes a second IC mounted thereon. The second IC comprises a second memory device that stores the first value. A third IC mounted on the printed circuit board is configured to provide a copy of the first value stored in the second memory device to the first IC for storage in the first memory device, wherein the third IC is configured to provide the copy of the first value to the first IC without condition.

摘要翻译： 一种用于无条件地将值加载到第一集成电路的第一存储器中的装置和方法，所述第一集成电路根据存储在第一存储器中的值以几种不同模式之一操作。 在一个实施例中，装置包括印刷电路板。 第一集成电路（IC）安装在印刷电路板上，其中第一IC包括第一存储器件，并且其中第一IC被配置为当第一值存储在第一存储器件中时以第一模式工作， 并且其中所述第一IC被配置为当第二值存储在所述第一存储器件中时以第二模式操作。 印刷电路板还包括安装在其上的第二IC。 第二IC包括存储第一值的第二存储器件。 安装在印刷电路板上的第三IC被配置为将存储在第二存储器件中的第一值的副本提供给第一IC以存储在第一存储器件中，其中第三IC被配置为提供第一IC 价值到第一个IC无条件。