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240 条记录 (耗时 0.048 秒)

    Multiple-gate transistors formed on bulk substrates
    41.
    发明授权
    Multiple-gate transistors formed on bulk substrates 有权
    形成在大量衬底上的多栅极晶体管

    公开(公告)号：US07863674B2

    公开(公告)日：2011-01-04

    申请号：US11645419

    申请日：2006-12-26

    申请人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L31/062

    CPC分类号： H01L29/66795 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853 ,  H01L2029/7857

    摘要： In one aspect, the present invention teaches a multiple-gate transistor 130 that includes a semiconductor fin 134 formed in a portion of a bulk semiconductor substrate 132. A gate dielectric 144 overlies a portion of the semiconductor fin 134 and a gate electrode 146 overlies the gate dielectric 144. A source region 138 and a drain region 140 are formed in the semiconductor fin 134 oppositely adjacent the gate electrode 144. In the preferred embodiment, the bottom surface 150 of the gate electrode 146 is lower than either the source-substrate junction 154 or the drain-substrate junction 152.

    摘要翻译： 在一个方面，本发明教导了一种多栅极晶体管130，其包括形成在体半导体衬底132的一部分中的半导体鳍片134.栅极电介质144覆盖在半导体鳍片134的一部分上，栅电极146覆盖 栅极电介质144.源极区域138和漏极区域140形成在与栅电极144相对的半导体鳍片134中。在优选实施例中，栅电极146的底表面150比源 - 154或漏极 - 衬底接合部152。

    Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
    42.
    发明授权
    Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors 有权
    使用部分耗尽和完全耗尽的晶体管配置的绝缘体上半导体SRAM

    公开(公告)号：US07301206B2

    公开(公告)日：2007-11-27

    申请号：US10700869

    申请日：2003-11-04

    申请人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01I29/76

    CPC分类号： H01L27/1104 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/7854

    摘要： A static memory element includes a first inverter having an input coupled to a left bit node and an output coupled to a right bit node. A second inverter has an input coupled to the right bit node and an output coupled to the left right bit node. A first fully depleted semiconductor-on-insulator transistor has a drain coupled to the left bit node, and a second fully depleted semiconductor-on-insulator transistor has a drain coupled to the right bit node.

    摘要翻译： 静态存储元件包括具有耦合到左位节点的输入和耦合到右位节点的输出的第一反相器。 第二反相器具有耦合到右位节点的输入和耦合到左右位节点的输出。 第一完全耗尽的绝缘体上半导体晶体管具有耦合到左位节点的漏极，并且第二完全耗尽的绝缘体上半导体晶体管具有耦合到右位节点的漏极。

    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
    44.
    发明授权
    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement 有权
    应变平衡结构具有拉伸应变硅通道和压缩应变硅 - 锗通道，用于CMOS性能提升

    公开(公告)号：US07238989B2

    公开(公告)日：2007-07-03

    申请号：US11201990

    申请日：2005-08-11

    申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    IPC分类号： H01L27/01

    CPC分类号： H01L29/1054 ,  H01L21/84 ,  H01L27/1203

    摘要： A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile strain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

    摘要翻译： 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于覆盖SiGe层的硅层中，允许NMOS沟道区存在于双层拉伸应变增强下的硅层中 电子迁移率。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

    Methods and Structures for Planar and Multiple-Gate Transistors Formed on SOI
    45.
    发明申请
    Methods and Structures for Planar and Multiple-Gate Transistors Formed on SOI 有权
    在SOI上形成的平面和多栅极晶体管的方法和结构

    公开(公告)号：US20070134860A1

    公开(公告)日：2007-06-14

    申请号：US11676480

    申请日：2007-02-19

    申请人： Fu-Liang Yang ,  Yee-Chia Yeo ,  Chenming Hu

    发明人： Fu-Liang Yang ,  Yee-Chia Yeo ,  Chenming Hu

    IPC分类号： H01L21/84

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

    摘要： A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of the semiconductor layer has a second thickness. The second thickness is larger than the first thickness. The first transistor has a first active region formed from the first portion of the semiconductor layer. The second transistor has a second active region formed from the second portion of the semiconductor layer. The first transistor may be a planar transistor and the second transistor may be a multiple-gate transistor, for example.

    摘要翻译： 半导体器件包括绝缘体层，半导体层，第一晶体管和第二晶体管。 半导体层覆盖绝缘体层。 半导体层的第一部分具有第一厚度。 半导体层的第二部分具有第二厚度。 第二厚度大于第一厚度。 第一晶体管具有由半导体层的第一部分形成的第一有源区。 第二晶体管具有由半导体层的第二部分形成的第二有源区。 第一晶体管可以是平面晶体管，例如，第二晶体管可以是多栅极晶体管。

    Methods and structures for planar and multiple-gate transistors formed on SOI
    46.
    发明授权
    Methods and structures for planar and multiple-gate transistors formed on SOI 有权
    在SOI上形成的平面和多栅极晶体管的方法和结构

    公开(公告)号：US07180134B2

    公开(公告)日：2007-02-20

    申请号：US10823158

    申请日：2004-04-13

    申请人： Fu-Liang Yang ,  Yee-Chia Yeo ,  Chenming Hu

    发明人： Fu-Liang Yang ,  Yee-Chia Yeo ,  Chenming Hu

    IPC分类号： H01L27/01 ,  H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

    摘要： A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of the semiconductor layer has a second thickness. The second thickness is larger than the first thickness. The first transistor has a first active region formed from the first portion of the semiconductor layer. The second transistor has a second active region formed from the second portion of the semiconductor layer. The first transistor may be a planar transistor and the second transistor may be a multiple-gate transistor, for example.

    摘要翻译： 半导体器件包括绝缘体层，半导体层，第一晶体管和第二晶体管。 半导体层覆盖绝缘体层。 半导体层的第一部分具有第一厚度。 半导体层的第二部分具有第二厚度。 第二厚度大于第一厚度。 第一晶体管具有由半导体层的第一部分形成的第一有源区。 第二晶体管具有由半导体层的第二部分形成的第二有源区。 第一晶体管可以是平面晶体管，例如，第二晶体管可以是多栅极晶体管。

    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
    48.
    发明申请
    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement 有权
    应变平衡结构具有拉伸应变硅通道和压缩应变硅 - 锗通道，用于CMOS性能提升

    公开(公告)号：US20050272188A1

    公开(公告)日：2005-12-08

    申请号：US11201990

    申请日：2005-08-11

    申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L31/109

    CPC分类号： H01L29/1054 ,  H01L21/84 ,  H01L27/1203

    摘要： A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile strain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

    摘要翻译： 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于覆盖SiGe层的硅层中，允许NMOS沟道区存在于双层拉伸应变增强下的硅层中 电子迁移率。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

    CMOS SRAM cell configured using multiple-gate transistors
    49.
    发明授权
    CMOS SRAM cell configured using multiple-gate transistors 有权
    使用多栅极晶体管配置的CMOS SRAM单元

    公开(公告)号：US06864519B2

    公开(公告)日：2005-03-08

    申请号：US10305728

    申请日：2002-11-26

    申请人： Yee-Chia Yeo ,  Chenming Hu ,  Fu-Liang Yang

    发明人： Yee-Chia Yeo ,  Chenming Hu ,  Fu-Liang Yang

    IPC分类号： H01L21/336 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

    CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785

    摘要： A complementary metal-oxide-semiconductor static random access memory cell that is formed by a pair of P-channel multiple-gate field-effect transistors (P-MGFETs), a pair of N-channel multiple-gate field-effect transistors (N-MGFETs), a second pair of N-MGFETs that has a drain respectively connected to a connection linking the respective drain of the N-MGFET of the first pair of N-MGFET to the drain of the P-MGFET of the pair of P-MGFETs; a pair of complementary bit lines, each respectively connected to the source of the N-MGFET of the second pair of N-MGFETS; and a word line connected to the gates of the N-MGFETs of the second pair of N-MGFETs.

    摘要翻译： 由一对P沟道多栅极场效应晶体管（P-MGFET），一对N沟道多栅极场效应晶体管（N）构成的互补金属氧化物半导体静态随机存取存储单元 -MGFET），第二对N-MGFET，其漏极分别连接到将第一对N-MGFET的N-MGFET的相应漏极连接到该对P-MGFET的漏极的连接 -MGFETs 一对互补位线，分别连接到第二对N-MGFETS的N-MGFET的源极; 以及连接到第二对N-MGFET的N-MGFET的门的字线。