公开(公告)号：US20070073448A1

公开(公告)日：2007-03-29

申请号：US11583885

申请日：2006-10-20

Applicant: Chisaki Takubo ,  Hiroji Yamada ,  Kazuhiro Mochizuki ,  Kenichi Tanaka ,  Tomonori Tanoue ,  Hiroyuki Uchiyama

Inventor： Chisaki Takubo ,  Hiroji Yamada ,  Kazuhiro Mochizuki ,  Kenichi Tanaka ,  Tomonori Tanoue ,  Hiroyuki Uchiyama

IPC: G05D1/10

CPC classification number: H01L21/30617 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/66318 ,  H01L29/7371

Abstract: A semiconductor device capable of overcoming a drawback due to the shape of a concave portion present in the zinc blende type compound semiconductor substrate in which the area of the bottom is larger than the surface in the cross sectional shape, as well as a manufacturing method thereof. A hole or step present in the semiconductor substrate constituting the semiconductor device is formed into a normal mesa shape irrespective of the orientation of the crystals on the surface of the semiconductor substrate. A wet etching solution having an etching rate for a portion below the etching mask higher than that in the direction of the depth of the semiconductor substrate is used.

Abstract translation: 一种半导体器件及其制造方法，其能够克服存在于闪锌矿型化合物半导体衬底中的凹部的形状的缺陷，其中底部的面积大于截面形状的表面，以及其制造方法 。 存在于构成半导体器件的半导体衬底中的孔或台阶形成为正常台面形状，而与半导体衬底的表面上的晶体取向无关。 使用对蚀刻掩模下方的蚀刻速率比半导体衬底的深度方向的蚀刻速度更高的湿蚀刻溶液。

公开(公告)号：US20060163696A1

公开(公告)日：2006-07-27

申请号：US11208561

申请日：2005-08-23

Applicant: Kazuhiro Mochizuki ,  Shigehisa Tanaka ,  Tomonori Tanoue

Inventor： Kazuhiro Mochizuki ,  Shigehisa Tanaka ,  Tomonori Tanoue

IPC: H01L27/082

CPC classification number: H01L29/7606 ,  H01L29/2003

Abstract: The most important task in realizing a downsized and low cost THz band spectroscopic and fluoroscopic instrument is to achieve downsizing and cost reduction of oscillators used in the instrument. A metal base transistor is used for an active element of the oscillator. In order to improve the maximum oscillation frequency of the transistor to several THZ, InN having a high electron saturation velocity or a material mainly composed of InN is used for a collector layer. In order to obtain characteristics with excellent reproducibility, it is useful to insert InGaN into an interface between the collector layer and the base layer. Using the metal base transistor of the present invention makes it possible to constitute an oscillator allowing a THz band oscillation. Further, the present invention provides a spectroscopic instrument applying this oscillator to at least one of a signal source and a local oscillator.

Abstract translation: 实现小型化，低成本的太赫兹频带光谱和荧光检测仪器最重要的任务是实现仪器中使用的振荡器的小型化和降低成本。 金属基极晶体管用于振荡器的有源元件。 为了将晶体管的最大振荡频率提高到几个THZ，具有高电子饱和速度的InN或主要由InN组成的材料用于集电极层。 为了获得具有优异再现性的特性，将InGaN插入到集电极层和基极层之间的界面是有用的。 使用本发明的金属基极晶体管可以构成允许THz频带振荡的振荡器。 此外，本发明提供了一种将该振荡器应用于信号源和本地振荡器中的至少一个的分光仪器。

公开(公告)号：US06853243B2

公开(公告)日：2005-02-08

申请号：US10222830

申请日：2002-08-19

Applicant: Kenji Sekine ,  Tomonori Tanoue ,  Osamu Kagaya

Inventor： Kenji Sekine ,  Tomonori Tanoue ,  Osamu Kagaya

IPC: H03F3/60 ,  H03F1/02 ,  H03F3/68 ,  H03F3/72 ,  H04B1/04 ,  H03F1/14 ,  H03G3/20

CPC classification number: H03F3/72 ,  H03F2200/429 ,  H03F2203/7236

Abstract: To provide a high frequency amplifying apparatus for reducing a phase change caused in switching to a different output level, a variable phase shifter is provided at at least one location of respective paths rearward from a branching circuit for switching a path on a high output side having an amplifier using a first semiconductor device at an output stage and a path on a low output side having an amplifier using a second semiconductor device with a smaller output than the first semiconductor device on an output stage in accordance with a desired output level. After branching and a phase length of the variable phase shifter is set to a pre-determined value such that passing phase lengths of the respective paths become substantially the same by passing either of the paths.

Abstract translation: 为了提供一种用于减少在切换到不同输出电平时引起的相位变化的高频放大装置，在分路电路后面的相应路径的至少一个位置设置可变移相器，用于切换具有 根据期望的输出电平，在输出级使用第一半导体器件的放大器和低输出侧的路径，具有在输出级上具有比第一半导体器件更小的输出的第二半导体器件的放大器。 在分支之后，将可变移相器的相位长度设置为预定值，使得各个路径的通过相位长度通过通过任一路径变得基本相同。

公开(公告)号：US5604835A

公开(公告)日：1997-02-18

申请号：US361681

申请日：1994-12-22

Applicant: Tohru Nakamura ,  Tomonori Tanoue ,  Takeshi Kato ,  Mitsuo Takeda

Inventor： Tohru Nakamura ,  Tomonori Tanoue ,  Takeshi Kato ,  Mitsuo Takeda

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/125 ,  G02B6/13 ,  G02B6/132 ,  G02B6/10

CPC classification number: G02B6/125 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/132

Abstract: An integrated optical waveguide device includes a substrate, and an optical waveguide which is formed in the form of projection or is formed in a trench formed in the substrate. Each optical waveguide has a first optical area made of a first optical material and a second optical area which is made of a second optical material and is surrounded by the first optical area. The optical waveguides are arranged on both side faces of the projection or trench.

Abstract translation: 集成光波导装置包括基板和形成为突起形状或形成在形成于基板中的沟槽中的光波导。 每个光波导具有由第一光学材料制成的第一光学区域和由第二光学材料制成并被第一光学区域包围的第二光学区域。 光波导布置在突起或沟槽的两个侧面上。

公开(公告)号：US5229623A

公开(公告)日：1993-07-20

申请号：US746288

申请日：1991-08-13

Applicant: Tomonori Tanoue ,  Hiroshi Mizuta ,  Susumu Takahashi

Inventor： Tomonori Tanoue ,  Hiroshi Mizuta ,  Susumu Takahashi

IPC: G02F3/02 ,  G06N3/063 ,  G06N3/067 ,  G11C11/56

CPC classification number: B82Y10/00 ,  G02F3/028 ,  G06N3/0635 ,  G06N3/0675 ,  G11C11/56 ,  G11C13/04 ,  G11C2211/5614

Abstract: A semiconductor device is disclosed, which includes a multiple negative differential resistance element having negative differential resistance characteristics at at least two places in the current-voltage characteristics, and which is suitable for constructing a neural network having a high density integration and a high reliability.

Abstract translation: 公开了一种半导体器件，其包括在电流 - 电压特性中的至少两个位置具有负的差分电阻特性的多个负的差分电阻元件，并且适用于构建具有高密度集成和高可靠性的神经网络。

公开(公告)号：US5023687A

公开(公告)日：1991-06-11

申请号：US304210

申请日：1989-01-31

Applicant: Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi

Inventor： Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8226 ,  H01L21/8228 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/082 ,  H01L27/12 ,  H01L29/737

CPC classification number: H01L29/66318 ,  H01L21/8226 ,  H01L21/8252 ,  H01L27/0605

Abstract: A complementary semiconductor device is disclosed having a substrate and a four layer structure of pnpn provided on the substrate wherein the first three layers constitute a pnp-type bipolar transistor and the second to the fourth layer constitute an npn-type bipolar transistor. According to the present invention, the pnp- and npn-type transistor which are disposed on different portions of a principal surface of the substrate, respectively, can be produced concurrently by crystal growth and thus production steps are simple and yield is remarkably improved.

公开(公告)号：US4983532A

公开(公告)日：1991-01-08

申请号：US286710

申请日：1988-12-20

Applicant: Katsuhiko Mitani ,  Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi ,  Masayoshi Saito ,  Hiroshi Miyazaki ,  Fumio Murai

Inventor： Katsuhiko Mitani ,  Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi ,  Masayoshi Saito ,  Hiroshi Miyazaki ,  Fumio Murai

IPC: H01L29/205 ,  H01L21/331 ,  H01L29/73 ,  H01L29/737

CPC classification number: H01L29/66318 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/072 ,  Y10S148/10

Abstract: Microfabrication and large scale integration of a device can be realized by using a planar heterojunction bipolar transistor formed by a process comprising successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction, wherein a collector drawing-out metal layer is formed by the selective CVD method.

Abstract translation: 可以通过使用通过包括通过在化合物上的外延生长分别连续生长用作子集电极，集电极，基极和发射极的半导体层的工艺形成的平面异质结双极晶体管来实现器件的微结构和大规模集成 半导体衬底，其中发射极结和集电极结中的至少一个是异质结，其中通过选择性CVD法形成集电体引出金属层。

公开(公告)号：US08076974B2

公开(公告)日：2011-12-13

申请号：US12980627

申请日：2010-12-29

Applicant: Satoshi Tanaka ,  Tomonori Tanoue

Inventor： Satoshi Tanaka ,  Tomonori Tanoue

IPC: H03G3/30

CPC classification number: H03F3/19 ,  H03F1/0261 ,  H03F3/245 ,  H03F2200/393 ,  H03F2200/451

Abstract: An RF power amplifier has a final-stage amplifier stage which generates an RF transmit output signal, a signal detector which detects an RF transmit output level, a first detector, a second detector and a control circuit. The final-stage amplifier stage includes a transistor and a load element and performs saturation type nonlinear amplification and non-saturation type linear amplification. The first detector and the control circuit maintain the RF transmit output signal approximately constant with respect to a variation in load at an antenna at the saturation type nonlinear amplification. The second detector and the control circuit reduce an increase in the output voltage of the final stage transistor with respect to an overload state of the antenna at the non-saturation type linear amplification.

公开(公告)号：US20060157825A1

公开(公告)日：2006-07-20

申请号：US11376116

申请日：2006-03-16

Applicant: Yasunari Umemoto ,  Hideyuki Ono ,  Tomonori Tanoue ,  Yasuo Ohsone ,  Isao Ohbu ,  Chushiro Kusano ,  Atsushi Kurokawa ,  Masao Yamane

Inventor： Yasunari Umemoto ,  Hideyuki Ono ,  Tomonori Tanoue ,  Yasuo Ohsone ,  Isao Ohbu ,  Chushiro Kusano ,  Atsushi Kurokawa ,  Masao Yamane

IPC: H01L27/082

CPC classification number: H01L27/0825 ,  H01L27/0259 ,  H01L29/7371 ,  H01L2224/48091 ,  H01L2224/73265 ,  H03K17/08146 ,  H03K17/615 ,  H01L2924/00014

Abstract: The invention is directed to improve resistance to destruction of a semiconductor device. A protection circuit having a plurality of bipolar transistors which are Darlington connected between outputs (collector and emitter) of an amplification circuit of a high output is electrically connected in parallel with the amplification circuit. The amplification circuit has a plurality of unit HBTs (Heterojunction Bipolar Transistors) which are connected in parallel with each other. The protection circuit has a two-stage configuration including a first group of a protection circuit having a plurality of bipolar transistors Q1 to Q5 and a second group of a protection circuit having a plurality of bipolar transistors.

Abstract translation: 本发明旨在提高对半导体器件的破坏性。 具有连接在高输出的放大电路的输出（集电极和发射极）之间的达林顿的多个双极晶体管的保护电路与放大电路并联电连接。 放大电路具有彼此并联连接的多个单元HBT（异质结双极晶体管）。 保护电路具有包括具有多个双极型晶体管Q 1至Q 5的第一组保护电路和具有多个双极晶体管的第二组保护电路的两级配置。

公开(公告)号：US07078975B2

公开(公告)日：2006-07-18

申请号：US11247185

申请日：2005-10-12

Applicant: Kiichi Yamashita ,  Tomonori Tanoue ,  Shizuo Kondo

Inventor： Kiichi Yamashita ,  Tomonori Tanoue ,  Shizuo Kondo

IPC: H03G3/30

CPC classification number: H03F1/02 ,  H03F1/30 ,  H03F3/21 ,  H03G7/001 ,  H03G7/06

Abstract: The present invention provides a power amplifier module featuring that: its output power characteristic smoothly changes as the input control voltage changes; and its control sensitivity is stable over a wide dynamic range. By same means, idling current for gain setting is supplied to a single amplifier element or all of multiple stages of amplifier elements of the power amplifier module. By making this idling current behave so as to exponentially change, relative to input control voltage, the invention enables output power control proportional to the input control voltage.

Abstract translation: 本发明提供了一种功率放大器模块，其特征在于：其输出功率特性随着输入控制电压的变化而平滑地变化; 其控制灵敏度在宽动态范围内稳定。 通过同样的方式，用于增益设定的空载电流被提供给功率放大器模块的单个放大器元件或放大器元件的多个级的全部。 通过使该怠速电流相对于输入控制电压发生指数变化，本发明实现与输入控制电压成比例的输出功率控制。