公开(公告)号：US20220130817A1

公开(公告)日：2022-04-28

申请号：US17081807

申请日：2020-10-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG ,  Wei-Cheng LIN

IPC: H01L27/02 ,  H01L27/12 ,  H01L21/84 ,  H03K3/037

Abstract: An integrated circuit includes a first pair of power rails and a second pair of power rails that are disposed in a first layer, conductive lines disposed in a second layer above the first layer, and a first active area disposed in a third layer above the second layer. The first active area is arranged to overlap the first pair of power rails. The first active area is coupled to the first pair of power rails through a first line of the conductive lines and a first group of vias, and the first active area is coupled to the second pair of power rails through at least one second line of the conductive lines and a second group of vias different from the first group of vias.

公开(公告)号：US20210357565A1

公开(公告)日：2021-11-18

申请号：US17147923

申请日：2021-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shang-Wei FANG ,  Kam-Tou SIO ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG ,  Lee-Chung LU ,  Yi-Kan CHENG ,  Chung-Hsing WANG

IPC: G06F30/392 ,  G06F30/398

Abstract: A method of generating an IC layout diagram includes abutting a first row of cells with a second row of cells along a border, the first row including first and second active sheets, the second row including third and fourth active sheets, the active sheets extending along a row direction and having width values. The active sheets are overlapped with first through fourth back-side via regions, the first active sheet width value is greater than the third active sheet width value, a first back-side via region width values is greater than a third back-side via region width value, and a value of a distance from the first active sheet to the border is less than a minimum spacing rule for metal-like defined regions. At least one of abutting the first row with the second row or overlapping the active sheets with the back-side via regions is performed by a processor.

公开(公告)号：US20210225831A1

公开(公告)日：2021-07-22

申请号：US17225664

申请日：2021-04-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Chih-Liang CHEN ,  Hui-Ting YANG ,  Shun Li CHEN ,  Ko-Bin KAO ,  Chih-Ming LAI ,  Ru-Gun LIU ,  Charles Chew-Yuen YOUNG

IPC: H01L27/02 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423

Abstract: A system that generates a layout diagram has a processor that implements a method, the method including: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.

公开(公告)号：US20190019797A1

公开(公告)日：2019-01-17

申请号：US16126875

申请日：2018-09-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Charles Chew-Yuen YOUNG ,  Chin-Yuan TSENG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Ru-Gun LIU ,  Wei-Liang LIN ,  L. C. CHOU

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L27/1104 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device including multiple fins. At least a first set of fins among the multiple fins is substantially parallel. At least a second set of fins among the multiple fins is substantially collinear. For any given first and second fins of the multiple fins having corresponding first and second fin-thicknesses, the second fin-thickness is less than plus or minus about 50% of the first fin-thickness.