公开(公告)号：US11081447B2

公开(公告)日：2021-08-03

申请号：US16573817

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Yu-Chen Chan ,  Ming-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.

公开(公告)号：US10211097B2

公开(公告)日：2019-02-19

申请号：US15063358

申请日：2016-03-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Yen Huang ,  Kai-Fang Cheng ,  Chi-Lin Teng ,  Shao-Kuan Lee ,  Hai-Ching Chen

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.

公开(公告)号：US09799603B2

公开(公告)日：2017-10-24

申请号：US15007779

申请日：2016-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Fang Cheng ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Tien-I Bao ,  Jung-Hsun Tsai

IPC: H01L21/4763 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a cover layer covering a first inner wall of the first opening. The cover layer has a second opening exposing the first conductive structure. The cover layer includes a metal oxide. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the cover layer. The second conductive structure is electrically connected to the first conductive structure.

公开(公告)号：US09460988B2

公开(公告)日：2016-10-04

申请号：US13868140

申请日：2013-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/485 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/485 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76898 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.

公开(公告)号：US12278143B2

公开(公告)日：2025-04-15

申请号：US18359070

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hsiang-Wei Liu ,  Tai-I Yang ,  Chia-Tien Wu ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/528 ,  H01L29/45

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

公开(公告)号：US20230369225A1

公开(公告)日：2023-11-16

申请号：US18357286

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Yu-Chen Chan ,  Ming-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53276 ,  H01L21/76834 ,  H01L21/76802 ,  H01L23/5226 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/53295 ,  H01L21/76877 ,  H01L21/76805

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first conductive feature and a second conductive feature disposed in an interlayer dielectric (ILD) layer. The semiconductor structure includes a first graphene layer disposed over the first conductive feature and a second graphene layer disposed over a portion of the second conductive feature. An etch-stop layer (ESL) is horizontally interposed between the first graphene layer and the second graphene layer. A side surface of the first or the second graphene layer directly contacts a side surface of the ESL. A third conductive feature is electrically coupled to the second conductive feature. The third conductive feature is separated from the first graphene layer by a portion of the ESL, and the third conductive feature also directly contacts a top surface of the ESL.

公开(公告)号：US20230112282A1

公开(公告)日：2023-04-13

申请号：US18064561

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285

Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

公开(公告)号：US11527435B2

公开(公告)日：2022-12-13

申请号：US17443506

申请日：2021-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/76 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321

Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

公开(公告)号：US11450566B2

公开(公告)日：2022-09-20

申请号：US17121661

申请日：2020-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Yen Huang ,  Kai-Fang Cheng ,  Chi-Lin Teng ,  Shao-Kuan Lee ,  Hai-Ching Chen

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.

公开(公告)号：US20220165613A1

公开(公告)日：2022-05-26

申请号：US17671222

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.