公开(公告)号：US20240258261A1

公开(公告)日：2024-08-01

申请号：US18629641

申请日：2024-04-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L24/24 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/08265 ,  H01L2224/24011 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/25171 ,  H01L2224/32227 ,  H01L2224/73267 ,  H01L2224/83001

摘要： A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US11978714B2

公开(公告)日：2024-05-07

申请号：US18068064

申请日：2022-12-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L24/24 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/08265 ,  H01L2224/24011 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/25171 ,  H01L2224/32227 ,  H01L2224/73267 ,  H01L2224/83001

摘要： A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US20230350142A1

公开(公告)日：2023-11-02

申请号：US18347188

申请日：2023-07-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC分类号： G02B6/42 ,  H01L23/00

CPC分类号： G02B6/4255 ,  H01L24/16 ,  H01L24/81 ,  G02B6/4246 ,  G02B6/4243 ,  H01L2224/81815 ,  H01L2224/16148 ,  H01L23/481

摘要： A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

公开(公告)号：US11728254B2

公开(公告)日：2023-08-15

申请号：US16881211

申请日：2020-05-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shang-Yun Hou ,  Hsien-Pin Hu ,  Sao-Ling Chiu ,  Wen-Hsin Wei ,  Ping-Kang Huang ,  Chih-Ta Shen ,  Szu-Wei Lu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/13 ,  H01L23/5385 ,  H01L2224/023 ,  H01L2225/107

摘要： A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

公开(公告)号：US20230124804A1

公开(公告)日：2023-04-20

申请号：US18068064

申请日：2022-12-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00

摘要： A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US20220365278A1

公开(公告)日：2022-11-17

申请号：US17873779

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC分类号： G02B6/122

摘要： A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

公开(公告)号：US20210287956A1

公开(公告)日：2021-09-16

申请号：US17331945

申请日：2021-05-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wensen Hung ,  Szu-Po Huang ,  Hsiang-Fan Lee ,  Kim Hong Chen ,  Chi-Hsi Wu ,  Shin-Puu Jeng

IPC分类号： H01L23/36 ,  H01L23/04 ,  H01L23/10 ,  H01L25/065 ,  H01L23/367 ,  H01L23/42 ,  H01L23/498

摘要： A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

公开(公告)号：US20210193485A1

公开(公告)日：2021-06-24

申请号：US17194721

申请日：2021-03-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Wei-Yu Chen

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L23/495 ,  H01L25/18 ,  H01L21/683 ,  H01L23/498

摘要： A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

公开(公告)号：US20210098382A1

公开(公告)日：2021-04-01

申请号：US16927992

申请日：2020-07-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Ting Lin ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Szu-Wei Lu

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

摘要： A package structure includes a plurality of semiconductor dies, an insulating encapsulant, a redistribution layer and a plurality of connecting elements. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant in a build-up direction and electrically connected to the plurality of semiconductor dies, wherein the redistribution layer includes a plurality of conductive lines, a plurality of conductive vias and a plurality of dielectric layers alternately stacked, and a lateral dimension of the plurality of conductive vias increases along the build-up direction. The connecting elements are disposed in between the redistribution layer and the semiconductor dies, wherein the connecting elements includes a body portion joined with the semiconductor dies and a via portion joined with the redistribution layer, wherein a lateral dimension of the via portion decreases along the build-up direction.

公开(公告)号：US20210082894A1

公开(公告)日：2021-03-18

申请号：US16572619

申请日：2019-09-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Weiming Chris Chen ,  Chi-Hsi Wu ,  Chih-Wei Wu ,  Kuo-Chiang Ting ,  Szu-Wei Lu ,  Shang-Yun Hou ,  Ying-Ching Shih ,  Hsien-Ju Tsou ,  Cheng-Chieh Li

IPC分类号： H01L25/18 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L21/82 ,  H01L23/48 ,  H01L21/56

摘要： A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.