公开(公告)号：US11831127B2

公开(公告)日：2023-11-28

申请号：US17817017

申请日：2022-08-03

Applicant: Silanna Asia Pte Ltd

Inventor： Joseph H. Colles ,  Steven E. Rosenbaum ,  Stuart B. Molin

IPC: H01S5/026 ,  H01S5/042 ,  H01S5/0233 ,  H03K17/687 ,  H01S5/42 ,  H01S5/40

CPC classification number: H01S5/0428 ,  H01S5/0233 ,  H01S5/0261 ,  H03K17/6871 ,  H01S5/4031 ,  H01S5/423

Abstract: A laser diode driver includes a clock terminal to receive a clock signal, configuration terminals to receive configuration data, drive terminals, and charging terminals. A first charging terminal is operable to charge a source capacitor of a resonant circuit that includes the source capacitor, an inductor, and a bypass capacitor. Each drive terminal is operable to be directly electrically connected to an anode or cathode of a laser diode or to ground. A mode, output selection, and grouping of drive signals that are delivered to the laser diodes are configured based on the configuration data. The laser diode driver is operable to control a current flow through the resonant circuit to produce high-current pulses through the laser diodes, the high-current pulses corresponding to a peak current of a resonant waveform developed at respective anodes of the laser diodes, a timing of the high-current pulses being synchronized using the clock signal.

公开(公告)号：US20230369421A1

公开(公告)日：2023-11-16

申请号：US18350941

申请日：2023-07-12

Applicant: Silanna Asia Pte Ltd

Inventor： Stuart B. Molin ,  George Imthurn ,  James Douglas Ballard ,  Yashodhan Vijay Moghe

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  G01R19/00

CPC classification number: H01L29/402 ,  H01L29/407 ,  H01L29/66681 ,  H01L29/7823 ,  H01L29/7816 ,  H01L29/404 ,  H01L29/7826 ,  H01L29/7824 ,  H01L29/66674 ,  H01L29/7817 ,  H01L29/7835 ,  G01R19/0092 ,  H01L29/66613

Abstract: An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.

公开(公告)号：US11742396B2

公开(公告)日：2023-08-29

申请号：US17453928

申请日：2021-11-08

Applicant: Silanna Asia Pte Ltd

Inventor： Stuart B. Molin ,  George Imthurn ,  James Douglas Ballard ,  Yashodhan Vijay Moghe

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  G01R19/00

CPC classification number: H01L29/402 ,  G01R19/0092 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66613 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7823 ,  H01L29/7824 ,  H01L29/7826 ,  H01L29/7835

Abstract: An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.

公开(公告)号：US20220329043A1

公开(公告)日：2022-10-13

申请号：US17658477

申请日：2022-04-08

Applicant: Silanna Asia Pte Ltd

Inventor： Joseph H. Colles ,  Steven E. Rosenbaum ,  Stuart B. Molin

IPC: H01S5/042 ,  H01S5/42 ,  H01S5/068 ,  H01S5/026

Abstract: A pulsed laser diode array driver includes an inductor having a first terminal configured to receive a source voltage, a source capacitor coupled between the first terminal of the inductor and ground, a bypass capacitor connected between a second terminal of the inductor and ground, a bypass switch connected between the second terminal of the inductor and ground, a laser diode array with one or more rows of laser diodes, and one or more laser diode switches, each being connected between a respective row node of the laser diode array and ground. The laser diode switches and the bypass switch are configured to control a current flow through the inductor to produce respective high-current pulses through each row of the laser diode array, each of the high-current pulses corresponding to a peak current of a resonant waveform developed at that row of the laser diode array.

公开(公告)号：US11245247B2

公开(公告)日：2022-02-08

申请号：US17301009

申请日：2021-03-22

Applicant: Silanna Asia Pte Ltd

Inventor： Joseph H. Colles ,  Steven E. Rosenbaum ,  Stuart B. Molin

IPC: H01S5/026 ,  H01S5/068 ,  H01S5/40 ,  H01S5/042

Abstract: A pulsed laser diode driver includes an inductor having a first terminal configured to receive a source voltage. A source capacitor has a first terminal connected to the first terminal of the inductor to provide the source voltage. A bypass switch has a drain node connected to a second terminal of the inductor and to a first terminal of a bypass capacitor. A laser diode has an anode connected to the second terminal of the inductor and to the drain node of the bypass switch. A laser diode switch has a drain node connected to a cathode of the laser diode. The laser diode switch and the bypass switch control a current flow through the inductor to produce a high-current pulse through the laser diode, the high-current pulse corresponding to a peak current of a resonant waveform developed at the anode of the laser diode.

公开(公告)号：US20210305896A1

公开(公告)日：2021-09-30

申请号：US17303949

申请日：2021-06-10

Applicant: Silanna Asia Pte Ltd

Inventor： Joseph H. Colles ,  Steven E. Rosenbaum ,  Stuart B. Molin

IPC: H02M3/07 ,  H03K17/687 ,  H02M1/088

Abstract: A charge pump having only NMOS devices charges a plurality of capacitors to a parallel charged voltage level by electrically connecting the capacitors in parallel between an input voltage node and a ground by activating a plurality of first NMOS transistor switches and a plurality of second NMOS transistor switches and deactivating a plurality of third NMOS transistor switches. The charge pump then generates a series capacitor output voltage level at a capacitor series output node by electrically connecting and discharging the capacitors in series between the input voltage node and the capacitor series output node by activating the third NMOS transistor switches and deactivating the first NMOS transistor switches and the second NMOS transistor switches.

公开(公告)号：US11005455B2

公开(公告)日：2021-05-11

申请号：US16375053

申请日：2019-04-04

Applicant: Silanna Asia Pte Ltd

Inventor： Joseph H. Colles ,  Steven E. Rosenbaum ,  Stuart B. Molin

IPC: H03K3/017 ,  H03K5/04 ,  H03K7/08 ,  H03K3/023

Abstract: A width of a voltage pulse signal is directly proportional to a difference between first and second resistances in a pulse generator. The voltage pulse signal is generated with a ramp signal, two reference voltages, and two comparators. The first reference voltage is generated with the first resistance and a first current, and the second reference voltage is generated with the second resistance and a second current. The first comparator produces a first comparator output in response to the first reference voltage and the ramp signal, and the second comparator produces a second comparator output in response to the second reference voltage and the ramp signal. A logic circuitry generates the voltage pulse signal in response to the two comparator outputs.

公开(公告)号：US20210036608A1

公开(公告)日：2021-02-04

申请号：US16990277

申请日：2020-08-11

Applicant: Silanna Asia Pte Ltd

Inventor： Joseph H. Colles ,  Steven E. Rosenbaum ,  Stuart B. Molin

IPC: H02M3/07 ,  H03K17/687 ,  H02M1/088

Abstract: A charge pump having only NMOS devices charges a plurality of capacitors to a parallel charged voltage level by electrically connecting the capacitors in parallel between an input voltage node and a ground by activating a plurality of first NMOS transistor switches and a plurality of second NMOS transistor switches and deactivating a plurality of third NMOS transistor switches. The charge pump then generates a series capacitor output voltage level at a capacitor series output node by electrically connecting and discharging the capacitors in series between the input voltage node and the capacitor series output node by activating the third NMOS transistor switches and deactivating the first NMOS transistor switches and the second NMOS transistor switches.

公开(公告)号：US20180240740A1

公开(公告)日：2018-08-23

申请号：US15680034

申请日：2017-08-17

Applicant: Silanna Asia Pte Ltd

Inventor： Shanghui Larry Tu ,  Michael A. Stuber ,  Befruz Tasbas ,  Stuart B. Molin ,  Raymond Jiang

IPC: H01L23/495 ,  H01L27/12 ,  H01L23/535 ,  H01L23/00 ,  H01L23/522 ,  H01L25/00 ,  H01L21/48

Abstract: A semiconductor package includes a leadframe having perimeter package leads and electrical connectors, a single semiconductor die having a back-side electrical contact and front-side electrical contacts, an electrically conductive clip (“clip”), and a top semiconductor die having a frontside and a backside. The single semiconductor die includes two or more transistors. Two or more of the front-side electrical contacts of the semiconductor die are electrically coupled to and physically mounted to respective electrical contacts of the leadframe. An electrical contact surface of the clip is electrically coupled to and physically mounted to an electrical connector of the leadframe. Another electrical contact surface of the clip is physically mounted to and electrically coupled to the back-side electrical contact of the semiconductor die. The backside of the top semiconductor die is physically mounted to yet another surface of the electrically conductive clip.

公开(公告)号：US20180197808A1

公开(公告)日：2018-07-12

申请号：US15402099

申请日：2017-01-09

Applicant: Silanna Asia Pte Ltd

Inventor： Stuart B. Molin ,  Laxminarayan Sharma

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49524 ,  H01L21/4825 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00

Abstract: Conductive clip connection arrangements for semiconductor packages are disclosed. Some examples provide electrically conductive clip connection arrangements for semiconductor packages that improve electrical performance and fabrication reliability while maintaining compatibility with existing quality control processes. Some examples provide innovative conductive clip structures and die pad arrangements that broaden the range of options available for tailoring the physical configurations of one or more of the constituent conductive clips and/or die pads to achieve specific electrical performance targets.