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    MEMORY DEVICE INCLUDING VOLTAGE GENERATING CIRCUIT AND OPERATION METHOD OF MEMORY DEVICE
    44.
    发明申请
    MEMORY DEVICE INCLUDING VOLTAGE GENERATING CIRCUIT AND OPERATION METHOD OF MEMORY DEVICE 有权

    公开(公告)号：US20250087256A1

    公开(公告)日：2025-03-13

    申请号：US18418001

    申请日：2024-01-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoonjae Lee ,  Yeji Shin ,  Sang-Wan Nam ,  Sang-Won Shim

    IPC: G11C7/10

    Abstract: Disclosed is a memory device which includes a memory cell array that includes a plurality of memory cells, and a peripheral circuit configured to perform a plurality of operations on the memory cell array by using a plurality of operating voltages. The peripheral circuit includes a voltage generating circuit including a first pump block, a second pump block, and a common pump block. The voltage generating circuit connects the first pump block and the common pump block in parallel to generate a first operating voltage among the plurality of operating voltages and connects the common pump block and the second pump block in series to generate a second operating voltage among the plurality of operating voltages. The common pump block is configurable to match the first pump block, the second pump block, or both, as needed.

    Non-volatile memory device
    47.
    发明授权
    Non-volatile memory device 有权

    公开(公告)号：US11200952B2

    公开(公告)日：2021-12-14

    申请号：US16991821

    申请日：2020-08-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Won Park ,  Sang-Wan Nam ,  Ji Yeon Shin ,  Won Bo Shim ,  Jung-Yun Yun ,  Ji Ho Cho ,  Sang Gi Hong

    IPC: G11C16/10 ,  H01L25/065 ,  H01L25/18 ,  G11C16/04 ,  H01L23/00

    Abstract: A non-volatile memory device comprises a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region, and a control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines.

    Methods of erasing data in nonvolatile memory devices and nonvolatile memory devices performing the same
    48.
    发明授权
    Methods of erasing data in nonvolatile memory devices and nonvolatile memory devices performing the same 有权

    公开(公告)号：US11164637B2

    公开(公告)日：2021-11-02

    申请号：US17015525

    申请日：2020-09-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Wan Nam ,  Dong-Hun Kwak ,  Chi-Weon Yoon

    IPC: G11C16/04 ,  G11C16/16 ,  G11C8/12 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/14

    Abstract: A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit applies an erase voltage to an erase source terminal of the memory block, and applies a first voltage to a first selection line among a plurality of selection lines in the memory block. The first voltage is higher than the erase voltage. The first selection line is disposed closest to the erase source terminal among the plurality of selection lines and is used for selecting the memory block as an erase target block.

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