公开(公告)号：US20190067484A1

公开(公告)日：2019-02-28

申请号：US15995414

申请日：2018-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Hoon KIM ,  Dong Myoung KIM ,  Dong Suk SHIN ,  Seung Hun LEE ,  Cho Eun LEE ,  Hyun Jung LEE ,  Sung Uk JANG ,  Edward Nam Kyu CHO ,  Min-Hee CHOI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02

Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

公开(公告)号：US20170345945A1

公开(公告)日：2017-11-30

申请号：US15373065

申请日：2016-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hun LEE ,  Dong Woo KIM ,  Dong Chan SUH ,  Sun Jung KIM

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

公开(公告)号：US20160056269A1

公开(公告)日：2016-02-25

申请号：US14749037

申请日：2015-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Jung LEE ,  Bonyoung KOO ,  Sunjung KIM ,  Jongryeol YOO ,  Seung Hun LEE ,  Poren TANG

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/3085 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823807

Abstract: A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer.

Abstract translation: 制造半导体器件的方法包括在衬底上形成沟道层，在沟道层上形成牺牲层，在牺牲层上形成硬掩模图案，并使用硬掩模图案作为蚀刻掩模进行图案化处理，形成 通道部分具有​​暴露的顶表面。 通道和牺牲层可由硅锗形成，并且牺牲层的锗含量可高于沟道层的锗含量。