公开(公告)号：US20140253196A1

公开(公告)日：2014-09-11

申请号：US13784915

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Yang Du ,  Jing Xie ,  Kambiz Samadi

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2924/0002 ,  H03K3/0372 ,  H01L2924/00

Abstract: Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.

Abstract translation: 公开了一种单片三维（3D）集成电路（IC）（3DIC）和相关方法中的触发器。 在一个实施例中，为3DIC提供单个时钟源并且分配给3DIC内的元件。 通过选择性可控制的触发器提供延迟到时钟路径，以帮助提供同步操作。 在某些实施例中，提供了3D触发器，其包括设置在3DIC的第一层中的主锁存器。 主锁存器被配置为接收触发器输入和时钟输入，主锁存器被配置为提供主锁存器输出。 3D触发器还包括设置在3DIC的至少一个附加层中的至少一个从锁存器，所述至少一个从锁存器被配置为提供3DIC触发器输出。 3D触发器还包括将主锁存器输出耦合到从锁存器的输入端（MIV）的至少一个单片间隔器。

公开(公告)号：US20140131885A1

公开(公告)日：2014-05-15

申请号：US13753193

申请日：2013-01-29

Applicant: QUALCOMM INCORPORATED

Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Yang Du ,  Robert P. Gilmore

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  G06F17/5068 ,  H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Abstract translation: 硬宏包括限定硬宏区域并具有顶部和底部以及从顶部到底部的宏宏厚度的周边，硬宏包括从顶部到底部延伸穿过硬宏厚度的多个通孔。 还有一种具有顶层，底层和至少一个中间层的集成电路，顶层包括顶层导电迹线，中间层包括硬宏，底层包括底层导电迹线，其中顶部 层导电迹线通过延伸穿过硬宏的通孔连接到底层导电迹线。

公开(公告)号：US11385706B2

公开(公告)日：2022-07-12

申请号：US16119929

申请日：2018-08-31

Applicant: QUALCOMM Incorporated

Inventor： Yu Pu ,  Yang Du

IPC: G06F1/32 ,  G06F1/3287 ,  G06N3/04 ,  G06F1/3234 ,  G06F1/3296 ,  G06N3/063

Abstract: A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.

公开(公告)号：US11004780B2

公开(公告)日：2021-05-11

申请号：US16688057

申请日：2019-11-19

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Yang Du ,  Robert Philip Gilmore

IPC: H01L23/498 ,  H01L21/768 ,  G06F30/39

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

公开(公告)号：US10510651B2

公开(公告)日：2019-12-17

申请号：US16220764

申请日：2018-12-14

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Yang Du ,  Robert Philip Gilmore

IPC: H01L23/498 ,  H01L21/768 ,  G06F17/50

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

公开(公告)号：US20180286800A1

公开(公告)日：2018-10-04

申请号：US15472614

申请日：2017-03-29

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/522 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/528 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5286 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

公开(公告)号：US20180260360A1

公开(公告)日：2018-09-13

申请号：US15452299

申请日：2017-03-07

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Amin Ansari ,  Yang Du

IPC: G06F15/80 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F15/80 ,  G06F9/3012 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/384 ,  G06F9/3867 ,  G06F12/0875 ,  G06F15/76 ,  G06F15/803 ,  G06F2212/452 ,  H01L25/0657 ,  H01L27/0688

Abstract: Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs) and related methods are disclosed. In aspects disclosed herein, ICs are provided that include a central processing unit (CPU) having multiple processor cores (“cores”) to improve performance. To further improve CPU performance, the multiple cores can also be designed to communicate with each other to offload workloads and/or share resources for parallel processing, but at a communication overhead associated with passing data through interconnects which have an associated latency. To mitigate this communication overhead inefficiency, aspects disclosed herein provide the CPU with its multiple cores in a 3DIC. Because 3DICs can overlap different IC tiers and/or align similar components in the same IC tier, the cores can be designed and located between or within different IC tiers in a 3DIC to reduce communication distance associated with processor core communication to share workload and/or resources, thus improving performance of the multi-processor CPU design.

公开(公告)号：US20160351553A1

公开(公告)日：2016-12-01

申请号：US15231836

申请日：2016-08-09

Applicant: QUALCOMM Incorporated

Inventor： Yang Du

IPC: H01L25/18 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L21/77 ,  H01L21/8221 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2225/06544 ,  Y10T29/41 ,  H01L2924/00014

Abstract: Embodiments disclosed in the detailed description include a complete system-on-chip (SOC) solution using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) integration technology. The present disclosure includes example of the ability to customize layers within a monolithic 3DIC and the accompanying short interconnections possible between tiers through monolithic intertier vias (MIV) to create a system on a chip. In particular, different tiers of the 3DIC are constructed to support different functionality and comply with differing design criteria. Thus, the 3DIC can have an analog layer, layers with higher voltage threshold, layers with lower leakage current, layers of different material to implement components that need different base materials and the like. Unlike the stacked dies, the upper layers may be the same size as the lower layers because no external wiring connections are required.

公开(公告)号：US20160258996A1

公开(公告)日：2016-09-08

申请号：US14639511

申请日：2015-03-05

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Ratibor Radojcic ,  Yang Du

IPC: G01R31/28 ,  H01L27/06 ,  G01R19/165 ,  H01L23/58 ,  H01L23/64 ,  H01L21/66 ,  H01L23/48

CPC classification number: G01R31/2851 ,  G01R19/16533 ,  G01R31/2853 ,  G01R31/318513 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L23/585 ,  H01L23/647 ,  H01L27/0688

Abstract: Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems are disclosed. In one aspect, a TSV crack sensor circuit is provided in which doped rings for a plurality of TSVs are interconnected in parallel such that all interconnected TSV doped rings may be tested at the same time by providing a single current into the contacts of the interconnected doped rings. In another aspect, a TSV crack sensor circuit is provided including one or more redundant TSVs. Each doped ring for a corresponding TSV is tested independently, and a defective TSV may be replaced with a spare TSV whose doped ring is not detected to be cracked. This circuit allows for correction of a compromised 3DIC by replacing possibly compromised TSVs with spare TSVs.

Abstract translation: 公开了用于检测三维（3D）集成电路（IC）（3DIC）中的TSV裂纹的穿通硅通孔（TSV）裂纹传感器以及相关方法和系统。 在一个方面，提供一种TSV裂纹传感器电路，其中用于多个TSV的掺杂环并联互连，使得所有互连的TSV掺杂环可以同时测试，通过向互连的掺杂的触点提供单个电流 戒指。 另一方面，提供包括一个或多个冗余TSV的TSV裂纹传感器电路。 用于对应的TSV的每个掺杂环被独立地测试，并且可以用未检测到其掺杂环被破裂的备用TSV来替换有缺陷的TSV。 该电路允许通过用备用TSV替换可能受损的TSV来校正受损的3DIC。

公开(公告)号：US09343369B2

公开(公告)日：2016-05-17

申请号：US14280731

申请日：2014-05-19

Applicant: QUALCOMM Incorporated

Inventor： Yang Du ,  Karim Arabi

IPC: H01L23/48 ,  H01L21/822 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/50 ,  H01L27/06

CPC classification number: H01L25/0652 ,  H01L21/50 ,  H01L21/76895 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/83 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/0694 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/08146 ,  H01L2224/08147 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/83125 ,  H01L2224/83895 ,  H01L2224/9202 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/00014

Abstract: Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process.

Abstract translation: 公开了构造三维集成电路及相关系统的方法。 在一个方面，通过在保持基板上产生诸如晶体管的有源元件来构造第一层。 在有源元件上方形成互连金属层。 在互连金属层内形成金属焊盘。 也创建了第二层，并行或顺序。 第二层以与第一层大致相同的方式创建，然后被放置在第一层上，使得相应的金属焊盘对准并且被一层结合到另一层。 然后释放第二层的保持基板。 然后减薄第二层的背面，使得有源元件的背面（例如，晶体管中的栅极的背面）被暴露。 如果需要，可以添加另外的层，基本上重复该过程。