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公开(公告)号：US09697640B2
公开(公告)日：2017-07-04
申请号：US14257385
申请日：2014-04-21
Applicant: QUALCOMM Incorporated
Inventor： Juraj Obert , Vineet Goel , Ouns Mouri
CPC classification number: G06T15/06 , G06T2210/12
Abstract: At least one processor may organize a plurality of primitives in a hierarchical data structure. The at least one processor may rasterize a plurality of bounding volumes associated with non-root nodes of the hierarchical data structure to an off-screen render target. The at least one processor may determine a bounding volume that is intersected by a ray out of the plurality of bounding volumes. The at least one processor may determine a non-root node of the hierarchical data structure that is associated with the bounding volume as a start node in the hierarchical data structure to start traversal of the hierarchical data structure. The at least one processor may traverse the hierarchical data structure starting from the start node to determine the primitive that is intersected by the ray.
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公开(公告)号：US20170091895A1
公开(公告)日：2017-03-30
申请号：US15013714
申请日：2016-02-02
Applicant: QUALCOMM Incorporated
Inventor： Anirudh Rajendra Acharya , Gang Zhong , Vineet Goel
Abstract: Techniques are described with respect to preemption in which a graphics processing unit (GPU) may execute a first set of commands in response to receiving a draw call, the draw call defining a plurality of primitives that are to be rendered by the first set of commands, receive a preemption notification during execution of the first set of commands, and preempt the execution of the first set of commands, prior to completing the execution of the first set of commands to render the plurality of primitives of the draw call, for executing a second set of commands.
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公开(公告)号：US09412197B2
公开(公告)日：2016-08-09
申请号：US13830145
申请日：2013-03-14
Applicant: QUALCOMM Incorporated
Inventor： Vineet Goel , Andrew Evan Gruber , Donghyun Kim
CPC classification number: G06T15/80 , G06T15/00 , G06T15/005
Abstract: Aspects of this disclosure generally relate to a process for rendering graphics that includes performing, with a hardware shading unit of a graphics processing unit (GPU) designated for vertex shading, vertex shading operations to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit is configured to receive a single vertex as an input and generate a single vertex as an output. The process also includes performing, with the hardware shading unit of the GPU, a geometry shading operation to generate one or more new vertices based on one or more of the vertex shaded vertices, wherein the geometry shading operation operates on at least one of the one or more vertex shaded vertices to output the one or more new vertices.
Abstract translation: 本公开的方面通常涉及用于渲染图形的处理，其包括使用指定为顶点着色的图形处理单元（GPU）的硬件阴影单元执行遮蔽输入顶点的顶点着色操作，以便输出顶点着色顶点，其中 硬件单元被配置为接收单个顶点作为输入并且生成单个顶点作为输出。 该过程还包括利用GPU的硬件着色单元执行基于顶点着色顶点中的一个或多个以生成一个或多个新顶点的几何阴影操作，其中，几何阴影操作对一个 或多个顶点着色顶点，以输出一个或多个新顶点。
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公开(公告)号：US09330495B2
公开(公告)日：2016-05-03
申请号：US13841407
申请日：2013-03-15
Applicant: QUALCOMM Incorporated
Inventor： Vineet Goel , Usame Ceylan
CPC classification number: G06T17/20 , G06T9/00 , G06T11/203 , G06T2200/28
Abstract: The present disclosure provides for path rendering including receiving, with a graphics processing unit (GPU), data indicative of a path segment of a path to be rendered. The systems and methods render the path segment by performing a fill of the path segment, which includes tessellating the path segment into a first plurality of primitives including a triangle per primitive, storing a first plurality of primitives in a stencil buffer, and drawing a bounding box of the path segment and rendering the bounding box with a stencil test enabled. The systems and methods also stroke the path segment, including tessellating the path into a second plurality of primitives, re-tessellating the second plurality of primitives, cutting the second plurality of primitives according to a dash pattern, creating a cap at a location of a cut, and creating a triangulation of a stroke and rasterizing the stroke based on the triangulation.
Abstract translation: 本公开提供路径渲染，包括用图形处理单元（GPU）接收指示要呈现的路径的路径段的数据。 系统和方法通过执行路径段的填充来呈现路径段，其包括将路径段细分为包括每个图元的三角形的第一多个图元，将第一多个图元存储在模版缓冲区中，以及绘制边界 框的路径段，并渲染了启用了模板测试的边界框。 所述系统和方法还中断路径段，包括将路径细分为第二多个基元，重新镶嵌第二多个图元，根据破折号图案切割第二多个图元，在第 切割，并创建一个中风的三角测量，并基于三角测量光栅化中风。
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公开(公告)号：US09275498B2
公开(公告)日：2016-03-01
申请号：US13841637
申请日：2013-03-15
Applicant: QUALCOMM Incorporated
Inventor： Usame Ceylan , Vineet Goel
CPC classification number: G06T17/20 , G06T9/00 , G06T11/203 , G06T2200/28
Abstract: A tessellation unit of a graphics processing unit (GPU) determines domain coordinates for vertices of a received primitive. The tessellation unit outputs the determined domain coordinates for the vertices. The tessellation unit further determines that a domain type for the received primitive is not one of tri, isoline, or quad domain, and outputs information indicative of a graphical feature associated with one or more of the determined domain coordinates when the domain type is not one of the tri, isoline, or quad domain.
Abstract translation: 图形处理单元（GPU）的细分单元确定接收到的基元的顶点的域坐标。 细分单元输出确定的顶点的域坐标。 细分单元进一步确定所接收到的基元的域类型不是三维，等距或四角域中的一个，并且当域类型不是一个时，输出指示与一个或多个所确定的域坐标相关联的图形特征的信息 的三角形，等距线或四角形域。
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Patent Agency Ranking
公开(公告)号：US20140210819A1
公开(公告)日：2014-07-31
申请号：US13754005
申请日：2013-01-30
Applicant: QUALCOMM INCORPORATED
Inventor： Chunhui Mei , Nariman Moezzi Madani , Vineet Goel , Usame Ceylan , Guofang Jiao
IPC: G06T17/20
CPC classification number: G06T17/20 , G06T15/005
Abstract: Systems and methods for a tessellation are described. For tessellation, a tessellation unit may divide a domain into a plurality of portions, where at least one portion is a contiguous portion. The tessellation unit may output domain coordinates of primitives along diagonal strips within the contiguous portion to increase the likelihood that patch coordinates that correspond to the domain coordinates are stored in a reuse buffer.
Abstract translation: 描述了细分的系统和方法。 为了细分，镶嵌单元可以将域划分成多个部分，其中至少一个部分是连续部分。 细分单元可以输出连续部分内沿着对角条纹的基元的域坐标，以增加对应于域坐标的修补坐标被存储在重用缓冲器中的可能性。
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公开(公告)号：US20140043341A1
公开(公告)日：2014-02-13
申请号：US13787363
申请日：2013-03-06
Applicant: QUALCOMM INCORPORATED
Inventor： Vineet Goel , Usame Ceylan
IPC: G06T1/00
CPC classification number: G06T1/00 , G06T11/203 , G06T2200/28
Abstract: This disclosure is directed to techniques for performing GPU-accelerated path rendering. A GPU is described that is configured to receive data indicative of a path segment of a path to be rendered, tessellate the path segment into a plurality of primitives, and render at least one of a fill area and a stroke area for the path segment based on the plurality of primitives. The techniques of this disclosure may be used to improve the performance of path rendering operations, to reduce memory bandwidth requirements needed to perform path rendering operations, and/or to reduce the memory footprint needed to perform path rendering operations.
Abstract translation: 本公开涉及用于执行GPU加速路径渲染的技术。 描述了被配置为接收指示要渲染的路径的路径段的数据的GPU，将路径段细分为多个基元，并且基于路径段呈现填充区域和笔划区域中的至少一个， 在多个基元上。 本公开的技术可以用于改善路径渲染操作的性能，以减少执行路径渲染操作所需的存储器带宽需求，和/或减少执行路径渲染操作所需的存储器占用空间。
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公开(公告)号：US20130265307A1
公开(公告)日：2013-10-10
申请号：US13829900
申请日：2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： Vineet Goel , Andrew E. Gruber
IPC: G06T15/80
Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes designating a hardware shading unit of a graphics processing unit (GPU) to perform first shading operations associated with a first shader stage of a rendering pipeline. The process also includes switching operational modes of the hardware shading unit upon completion of the first shading operations. The process also includes performing, with the hardware shading unit of the GPU designated to perform the first shading operations, second shading operations associated with a second, different shader stage of the rendering pipeline.
Abstract translation: 本公开的方面涉及用于渲染图形的过程，其包括指定图形处理单元（GPU）的硬件着色单元，以执行与呈现流水线的第一着色器阶段相关联的第一着色操作。 该过程还包括在第一着色操作完成时切换硬件着色单元的操作模式。 该过程还包括使用被指定为执行第一着色操作的GPU的硬件着色单元执行与渲染管线的第二不同着色器阶段相关联的第二着色操作。
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公开(公告)号：US20130194286A1
公开(公告)日：2013-08-01
申请号：US13747947
申请日：2013-01-23
Applicant: QUALCOMM Incorporated
Inventor： Alexei V. Bourd , Vineet Goel
IPC: G06T1/60
CPC classification number: G06T1/60 , G06F9/5038 , G06F9/52 , G06F9/544 , G06T1/20 , G09G5/001 , G09G5/363 , G09G2360/10 , G09G2360/121
Abstract: The techniques are generally related to management of buffers with a management unit that resides within an integrated circuit that includes a graphics processing unit (GPU). The management unit may ensure proper access to the buffers by the programmable compute units of the GPU to allow the GPU to execute kernels on the programmable compute units in a pipeline fashion.
Abstract translation: 这些技术通常涉及具有位于包括图形处理单元（GPU）的集成电路内的管理单元的缓冲器的管理。 管理单元可以确保由GPU的可编程计算单元适当地访问缓冲器，以允许GPU以管道方式在可编程计算单元上执行内核。
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公开(公告)号：US10535185B2
公开(公告)日：2020-01-14
申请号：US13830075
申请日：2013-03-14
Applicant: QUALCOMM Incorporated
Inventor： Vineet Goel , Andrew Evan Gruber , Donghyun Kim
Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.
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