公开(公告)号：US09966149B2

公开(公告)日：2018-05-08

申请号：US15450055

申请日：2017-03-06

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Kangho Lee ,  Seung H. Kang ,  Xia Li ,  Wah Nam Hsu

IPC: G11C11/00 ,  G11C17/02 ,  G11C11/16

CPC classification number: G11C17/18 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  G11C17/16 ,  G11C17/165

Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

公开(公告)号：US09666274B2

公开(公告)日：2017-05-30

申请号：US15244456

申请日：2016-08-23

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim

IPC: G11C11/00 ,  G11C13/00 ,  G11C5/06 ,  G11C7/08 ,  G11C29/02

CPC classification number: G11C13/004 ,  G11C5/063 ,  G11C7/08 ,  G11C11/1673 ,  G11C13/0038 ,  G11C13/0069 ,  G11C29/026 ,  G11C29/028 ,  G11C2013/0054

Abstract: A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits.

公开(公告)号：US09455014B1

公开(公告)日：2016-09-27

申请号：US14818809

申请日：2015-08-05

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Taehyun Kim ,  Sungryul Kim ,  Seung Hyuk Kang ,  Jung Pill Kim

IPC: G11C11/00 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  G11C29/44

CPC classification number: G11C11/1675 ,  G11C7/12 ,  G11C11/1659 ,  G11C11/1677 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44 ,  G11C29/52

Abstract: Aspects for adjusting resistive memory write driver strength based on write error rate (WER) are disclosed. In one aspect, a write driver strength control circuit is provided to adjust a write current provided to a resistive memory based on a WER of the resistive memory. The write driver strength control circuit includes a tracking circuit configured to determine the WER of the resistive memory based on write operations performed on resistive memory elements. The write driver strength control circuit includes a write current calculator circuit configured to compare the WER to a target WER that represents the desired yield performance level of the resistive memory. A write current adjust circuit in the write driver strength control circuit is configured to adjust the write current based on this comparison. The write driver strength control circuit adjusts the write current to perform write operations while reducing write errors associated with breakdown voltage.

Abstract translation: 公开了基于写入错误率（WER）调整电阻性​​存储器写入驱动器强度的方面。 一方面，提供写入驱动器强度控制电路，以基于电阻性存储器的WER来调整提供给电阻性存储器的写入电流。 写驱动器强度控制电路包括跟踪电路，其被配置为基于对电阻性存储器元件执行的写入操作来确定电阻性存储器的WER。 写驱动器强度控制电路包括写入电流计算器电路，其被配置为将WER与表示电阻性存储器的期望产出性能水平的目标WER进行比较。 写入驱动器强度控制电路中的写入电流调整电路被配置为基于该比较来调整写入电流。 写入驱动器强度控制电路调节写入电流以执行写入操作，同时减少与击穿电压相关联的写入错误。

公开(公告)号：US09455013B2

公开(公告)日：2016-09-27

申请号：US14992753

申请日：2016-01-11

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00 ,  G11C7/14 ,  G11C11/15 ,  G11C29/02

CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/004 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0042 ,  G11C2013/0054

Abstract: A method includes, at a resistive memory device, determining an average effective reference resistance level based on a first effective reference resistance and a second effective reference resistance. The first effective reference resistance is based on a first set of reference cells of the resistive memory device and the second effective reference resistance is based on a second set of reference cells of the resistive memory device. The method includes trimming a reference resistance at least partially based on the average effective reference resistance level. Trimming the reference resistance includes, in response to determining that the first effective reference resistance is not substantially equal to the average effective reference resistance level, modifying one or more states of one or more magnetic tunnel junction devices associated with the first effective reference resistance.

Abstract translation: 一种方法包括在电阻式存储器件中，基于第一有效参考电阻和第二有效参考电阻来确定平均有效参考电阻电平。 第一有效参考电阻基于电阻性存储器件的第一组参考单元，第二有效参考电阻基于电阻式存储器件的第二组参考单元。 该方法包括至少部分地基于平均有效参考电阻电平来修整参考电阻。 响应于确定第一有效参考电阻基本上不等于平均有效参考电阻电平，修整参考电阻包括修改与第一有效参考电阻相关联的一个或多个磁性隧道结装置的一个或多个状态。

公开(公告)号：US20160240237A1

公开(公告)日：2016-08-18

申请号：US14620487

申请日：2015-02-12

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1677 ,  G11C2013/0078

Abstract: Aspects of adjusting resistive memory write driver strength based on a mimic resistive memory write operation are disclosed. In one aspect, a write driver adjustment circuit is provided to adjust a write current provided by a write driver to a resistive memory for write operations. The write driver adjustment circuit includes a mimic write driver configured to provide a mimic write current that mimics the write current provided to the resistive memory. The mimic write current is applied to a mimic resistive memory that contains mimic resistive memory elements that mimic a resistance distribution of the resistive memory. When the mimic write current is applied, a mimic voltage is generated across the mimic resistive memory elements. The write driver adjustment circuit is configured to adjust the write current based on the mimic voltage so that the write current is sufficient for write operations, but low enough to reduce breakdown.

Abstract translation: 公开了基于模拟电阻式存储器写入操作来调节电阻性存储器写入驱动器强度的方面。 一方面，提供写入驱动器调整电路以将由写入驱动器提供的写入电流调整到用于写入操作的电阻性存储器。 写驱动器调整电路包括模拟写驱动器，其配置为提供模拟写入电流，模拟写入电流提供给电阻存储器。 模拟写入电流被施加到模拟电阻性存储器，其包含模拟电阻性存储器的电阻分布的模拟电阻存储器元件。 当应用模拟写入电流时，在模拟电阻存储器元件之间产生模拟电压。 写入驱动器调整电路被配置为基于模拟电压来调整写入电流，使得写入电流对于写入操作是足够的，但是足够低以减少击穿。

公开(公告)号：US09372750B2

公开(公告)日：2016-06-21

申请号：US14070480

申请日：2013-11-01

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Jung Pill Kim ,  Seung Hyuk Kang ,  Taehyun Kim

IPC: G06F11/10 ,  G06F12/02 ,  G06F11/07

CPC classification number: G06F11/1008 ,  G06F11/076 ,  G06F11/0766 ,  G06F11/1048 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7204 ,  G06F2212/7209

Abstract: A memory module comprising a non-volatile cell array and a re-mapper. A page map table is stored in the non-volatile cell array, and includes mappings of old page addresses to new page addresses. The re-mapper is configured to direct memory operations referencing an old page address to the new page address that the old page address is mapped to. The mappings are created when a memory cell is determined to be in a failure state.

Abstract translation: 一种包括非易失性单元阵列和重新映射器的存储模块。 页面映射表存储在非易失性单元阵列中，并且包括旧页地址到新页地址的映射。 重映射器被配置为将引用旧页地址的内存操作定向到旧页地址被映射到的新页地址。 当确定存储器单元处于故障状态时，创建映射。

公开(公告)号：US09336847B2

公开(公告)日：2016-05-10

申请号：US14257794

申请日：2014-04-21

Applicant: QUALCOMM Incorporated

Inventor： Sungryul Kim ,  Taehyun Kim ,  Jung Pill Kim

IPC: G11C7/14 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/1659

Abstract: Methods and apparatus for generating a reference for use with a magnetic tunnel junction are provided. In an example, provided is a magnetoresistive read only memory including a magnetic tunnel junction (MTJ) storage element, a sense amplifier having a first input coupled to the MTJ storage element, and a reference resistance device coupled to a second input of the sense amplifier. The reference resistance device includes a plurality of groups of at least two reference MTJ devices. Each reference MTJ device in a respective group is coupled in parallel with each other reference MTJ device in the respective group. Each group is coupled in series with the other groups. This arrangement advantageously mitigates read disturbances and reference level variations, while saving power, reducing reference resistance device area, and increasing read speed.

Abstract translation: 提供了用于产生用于磁性隧道结的参考的方法和装置。 在一个例子中，提供了一种包括磁性隧道结（MTJ）存储元件的磁阻只读存储器，具有耦合到MTJ存储元件的第一输入的读出放大器和耦合到读出放大器的第二输入的参考电阻器件 。 参考电阻装置包括多组至少两个参考MTJ装置。 相应组中的每个参考MTJ设备与相应组中的每个其他参考MTJ设备并联耦合。 每个组与其他组串联。 这种布置有利于减轻读取干扰和参考电平变化，同时节省功率，减少参考电阻器件面积并增加读取速度。

公开(公告)号：US09262263B2

公开(公告)日：2016-02-16

申请号：US14088867

申请日：2013-11-25

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C29/00 ,  G06F11/10 ,  G06F12/00

CPC classification number: G06F11/102 ,  G06F11/1064 ,  G06F12/00

Abstract: A particular device includes a resistance-based memory device, a tag random-access memory (RAM), and a bit recovery (BR) memory. The resistance-based memory device is configured to store a data value and error-correcting code (ECC) data associated with the data value. The tag RAM is configured to store information that maps memory addresses of a main memory to wordlines of a cache memory, where the cache memory includes the resistance-based memory device. The BR memory is configured to store additional error correction data associated with the data value, where the BR memory corresponds to a volatile memory device.

Abstract translation: 特定设备包括基于电阻的存储器件，标签随机存取存储器（RAM）和位恢复（BR）存储器。 基于电阻的存储器件被配置为存储与数据值相关联的数据值和纠错码（ECC）数据。 标签RAM被配置为存储将主存储器的存储器地址映射到高速缓冲存储器的字线的信息，其中高速缓冲存储器包括基于电阻的存储器件。 BR存储器被配置为存储与数据值相关联的附加纠错数据，其中BR存储器对应于易失性存储器设备。

公开(公告)号：US09251881B2

公开(公告)日：2016-02-02

申请号：US14040332

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00 ,  G11C7/14 ,  G11C11/15 ,  G11C29/02

CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/004 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0042 ,  G11C2013/0054

Abstract: A system and method to trim reference levels in a resistive memory is disclosed. In a particular embodiment, a resistive memory includes multiple sets of reference cells. The resistive memory also includes a reference resistance measurement circuit. A first set of reference cells is accessible by the reference resistance measurement circuit to measure a first effective reference resistance corresponding to the first set of reference cells. A second set of reference cells is accessible by the reference resistance measurement circuit to measure a second effective reference resistance corresponding to the second set of reference cells. The resistive memory also includes a trimming circuit configured to set a reference resistance based on the measured first effective resistance and the measured second effective resistance.

Abstract translation: 公开了一种在电阻性存储器中修整参考电平的系统和方法。 在特定实施例中，电阻性存储器包括多组参考单元。 电阻存储器还包括参考电阻测量电路。 第一组参考单元可由参考电阻测量电路访问，以测量对应于第一组参考单元的第一有效参考电阻。 第二组参考单元可由参考电阻测量电路访问，以测量对应于第二组参考单元的第二有效参考电阻。 电阻存储器还包括修整电路，其被配置为基于测量的第一有效电阻和所测量的第二有效电阻来设置参考电阻。

公开(公告)号：US09153307B2

公开(公告)日：2015-10-06

申请号：US14021674

申请日：2013-09-09

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/16 ,  G11C7/06 ,  G11C7/14 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/14 ,  G11C11/1659 ,  G11C13/0069

Abstract: An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells. Each of the four MTJ cells is coupled to a distinct word line. Each of the four MTJ cells includes an MTJ element and a single transistor. The single transistor of each particular MTJ cell is configured to enable read access to the MTJ element of the particular MTJ cell.

Abstract translation: 一种装置包括一组数据单元和耦合到该组数据单元的参考单元。 参考单元包括四个磁隧道结（MTJ）单元。 四个MTJ单元中的每一个耦合到不同的字线。 四个MTJ单元中的每一个包括MTJ元件和单个晶体管。 每个特定MTJ单元的单个晶体管被配置为使得能够读取访问特定MTJ单元的MTJ元件。