公开(公告)号：US10437552B2

公开(公告)日：2019-10-08

申请号：US15895965

申请日：2018-02-13

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Amit Gil ,  Oded Schnitzer

IPC: G10L19/018 ,  G06F3/16 ,  G10K11/16 ,  G10L19/012 ,  H03G3/34

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

公开(公告)号：US10089275B2

公开(公告)日：2018-10-02

申请号：US15168574

申请日：2016-05-31

Applicant: QUALCOMM Incorporated

Inventor： Ofer Rosenberg ,  Amit Gil ,  James Lionel Panian ,  Piyush Patel ,  Shaul Yohai Yifrach

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16

Abstract: Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) system is disclosed. A PCIe system includes a host system and at least one PCIe endpoint. The PCIe endpoint is configured to determine one or more transaction-specific attributes that can improve efficiency and performance of a predefined host transaction. In this regard, in one aspect, the PCIe endpoint encodes the transaction-specific attributes in a transaction layer packet (TLP) prefix of at least one PCIe TLP and provides the PCIe TLP to the host system. In another aspect, a PCIe root complex (RC) in the host system is configured to detect and extract the transaction-specific attributes from the TLP prefix of the PCIe TLP received from the PCIe endpoint. By communicating the transaction-specific attributes in the TLP prefix of the PCIe TLP, it is possible to improve efficiency and performance of the PCIe system without violating the existing PCIe standard.

公开(公告)号：US10073137B2

公开(公告)日：2018-09-11

申请号：US15226482

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Oren Reiss ,  Lior Amarilio ,  Amit Gil ,  Boaz Moskovich

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/2884 ,  G01R31/31705 ,  G01R31/3177 ,  G06F11/3656

Abstract: SoundWire-based embedded debugging in an electronic system is provided. In this regard, in one aspect, a SoundWire slave circuit receives a SoundWire data input signal over a SoundWire bus including two physical wires. The SoundWire data input signal includes a plurality of debug configuration bits in assigned SoundWire bitslots. The SoundWire slave circuit generates a plurality debug input bits required for debugging the SoundWire slave circuit based on the debug configuration bits received in the assigned SoundWire bitslots. In another aspect, the SoundWire slave circuit returns a SoundWire data output signal, which includes a debug output bit in an assigned SoundWire bitslot, over the SoundWire bus. By receiving debugging configurations and returning debugging results over the SoundWire bus, it is possible to debug the SoundWire slave circuit with a reduced number of physical pins, thus helping to reduce the overall pin count and footprint of the electronic device.

公开(公告)号：US20180167729A1

公开(公告)日：2018-06-14

申请号：US15894401

申请日：2018-02-12

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Amit Gil ,  Oded Schnitzer

IPC: H04R3/00 ,  G10L19/16 ,  G10L19/012 ,  H03G3/34 ,  G06F3/16 ,  G06F13/38

CPC classification number: H04R3/007 ,  G06F3/165 ,  G06F13/38 ,  G10L19/012 ,  G10L19/167 ,  H03G3/34 ,  H03G3/341 ,  H03G3/348

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

公开(公告)号：US09998573B2

公开(公告)日：2018-06-12

申请号：US15226429

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Tomer Rafael Ben-Chen ,  Amit Gil ,  Dan Gilboa Waizman ,  Deepak Jindal ,  Ayala Miller ,  Shaul Yohai Yifrach

IPC: H04L12/28 ,  H04L29/06 ,  H04L12/741 ,  H04L12/749

CPC classification number: H04L69/22 ,  H04L45/741 ,  H04L45/745 ,  H04L69/04 ,  H04L69/08 ,  H04L69/18 ,  H04L69/321

Abstract: Hardware-based packet processing circuitry is provided. In this regard, hardware-based packet processing circuitry includes header processing circuitry and payload processing circuitry. The hardware-based packet processing circuitry receives a header portion and a payload portion of an incoming packet in a first packet format. The header processing circuitry and the payload processing circuitry process the header portion and the payload portion to form a processed header portion and a processed payload portion, respectively. The hardware-based packet processing circuitry generates an outgoing packet in a second packet format based on the processed header portion and the processed payload portion. By processing the incoming packet separately in the header processing circuitry and the payload processing circuitry, it is possible to accelerate selected steps (e.g., ciphering/deciphering, compression/de-compression, checksum, etc.) of packet processing via dedicated hardware functional block(s), thus reducing computing resource requirement and overhead associated with software-based packet processing.

公开(公告)号：US20180038908A1

公开(公告)日：2018-02-08

申请号：US15226482

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Oren Reiss ,  Lior Amarilio ,  Amit Gil ,  Boaz Moskovich

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/2884 ,  G01R31/31705 ,  G01R31/3177 ,  G06F11/3656

Abstract: SoundWire-based embedded debugging in an electronic system is provided. In this regard, in one aspect, a SoundWire slave circuit receives a SoundWire data input signal over a SoundWire bus including two physical wires. The SoundWire data input signal includes a plurality of debug configuration bits in assigned SoundWire bitslots. The SoundWire slave circuit generates a plurality debug input bits required for debugging the SoundWire slave circuit based on the debug configuration bits received in the assigned SoundWire bitslots. In another aspect, the SoundWire slave circuit returns a SoundWire data output signal, which includes a debug output bit in an assigned SoundWire bitslot, over the SoundWire bus. By receiving debugging configurations and returning debugging results over the SoundWire bus, it is possible to debug the SoundWire slave circuit with a reduced number of physical pins, thus helping to reduce the overall pin count and footprint of the electronic device.

公开(公告)号：US09563398B2

公开(公告)日：2017-02-07

申请号：US15060503

申请日：2016-03-03

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Wietfeldt ,  George Wiley ,  Amit Gil

IPC: G06F13/40 ,  G06F5/06 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F5/065 ,  G06F9/455 ,  G06F13/385 ,  G06F13/4086 ,  G06F13/42 ,  G06F13/426 ,  G06F13/4286 ,  G06F2205/067

Abstract: A two wire interface is disclosed that serializes messaging signals and GPIO signals into frames transmitted over a transmit pin. The two wire interface is configured to perform flow control by monitoring a voltage for the transmit pin.

Abstract translation: 公开了将消息传送信号和GPIO信号串行化成通过传输引脚传输的帧的双线接口。 两线接口被配置为通过监视发送引脚的电压来执行流量控制。

公开(公告)号：US20160371208A1

公开(公告)日：2016-12-22

申请号：US15184124

申请日：2016-06-16

Applicant: QUALCOMM Incorporated

Inventor： Ofer Rosenberg ,  Amit Gil ,  James Lionel Panian ,  Piyush Patel ,  Shaul Yohai Yifrach

IPC: G06F13/24 ,  G06F13/42

Abstract: Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.

Abstract translation: 公开了扩展消息信号中断（MSI）数据。 在一个方面，MSI比特被修改为包括系统级标识符。 在示例性方面，MSI消息数据的高16位被修改为系统级标识符。 通过在MSI消息数据内提供系统级标识符，中断控制器可以验证中断源。

公开(公告)号：US20160259624A1

公开(公告)日：2016-09-08

申请号：US15060503

申请日：2016-03-03

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Wietfeldt ,  George Wiley ,  Amit Gil

IPC: G06F5/06 ,  G06F15/78 ,  G06F13/40 ,  G06F15/17 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F5/065 ,  G06F9/455 ,  G06F13/385 ,  G06F13/4086 ,  G06F13/42 ,  G06F13/426 ,  G06F13/4286 ,  G06F2205/067

Abstract: A two wire interface is disclosed that serializes messaging signals and GPIO signals into frames transmitted over a transmit pin. The two wire interface is configured to perform flow control by monitoring a voltage for the transmit pin.

Abstract translation: 公开了将消息传送信号和GPIO信号串行化成通过传输引脚传输的帧的双线接口。 两线接口被配置为通过监视发送引脚的电压来执行流量控制。

公开(公告)号：US09431077B2

公开(公告)日：2016-08-30

申请号：US13798803

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Amit Gil ,  Erez Tsidon ,  Yanru Li ,  Azzedine Touzni

IPC: G06F9/52 ,  G06F9/54 ,  G11C7/10 ,  G06F1/32 ,  G06F9/46 ,  G06F11/07

CPC classification number: G11C7/1075 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/462 ,  G06F9/463 ,  G06F9/52 ,  G06F9/544 ,  G06F11/0757 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

Abstract: Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data.

Abstract translation: 描述了使用多端口共享非易失性存储器的有效技术，其减少了诸如调制解调器控制处理器之类的专用功能特定处理器的存储器访问中的延迟。 调制解调器处理器抢占正在从多端口共享非易失性存储器闪存器件访问数据的主处理器，允许调制解调器处理器快速访问闪存设备中的数据。 抢占过程使用由寻求访问并中断处理器被抢占的处理器发起的门铃中断。 抢占后，主机处理器可以恢复或重新启动数据访问。 处理器的访问控制利用硬件信号量原子控制机制。 共享的非易失性存储器模块的功率控制包括至少一个不活动定时器，以指示何时可以安全地减少或关闭共享的非易失性存储器模块的电源电压。 共享内存的任何处理器可能会重新启动电源，从而可以快速访问数据。