公开(公告)号：US20160259743A1

公开(公告)日：2016-09-08

申请号：US15059009

申请日：2016-03-02

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Boaz Moskovich ,  Michael Zilbershtein

IPC: G06F13/36 ,  G06F13/42

CPC classification number: G06F13/36 ,  G06F13/4282 ,  G06F13/4291 ,  H04L47/72 ,  Y02D10/14 ,  Y02D10/151

Abstract: Full bandwidth communication buses are disclosed. While primarily focused on the Serial Low-power Inter-chip Media Bus (SLIMbus) communication bus, the concepts of the present disclosure may be extended to other communication buses. Exemplary aspects of the present disclosure utilize a reserved segment distribution code and a segment length to define a Segment Interval that is better-sized relative to raw data bits. By fitting the segment interval to the size of the raw data bits, bandwidth utilization is maximized, resulting in faster effective data transfers. Completion of such efficient data transfers may allow the communication bus to spend more time in a low-power mode and thus, conserve power. Additionally, such efficient data transfers may allow for better quality in presentation of multimedia content to the user.

Abstract translation: 全带宽通信总线被公开。 虽然主要关注于串行低功率片上媒体总线（SLIMbus）通信总线，但是本公开的概念可以扩展到其他通信总线。 本公开的示例性方面利用保留段分布代码和段长度来定义相对于原始数据位更好的段间隔。 通过将段间隔拟合为原始数据位的大小，带宽利用率最大化，从而实现更快的有效数据传输。 完成这种有效的数据传输可以允许通信总线在低功率模式下花费更多的时间，从而节省功率。 此外，这种有效的数据传输可以允许在向用户呈现多媒体内容方面更好的质量。

公开(公告)号：US09934178B2

公开(公告)日：2018-04-03

申请号：US15059009

申请日：2016-03-02

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Boaz Moskovich ,  Michael Zilbershtein

IPC: G06F13/36 ,  G06F13/42 ,  H04L12/911

CPC classification number: G06F13/36 ,  G06F13/4282 ,  G06F13/4291 ,  H04L47/72 ,  Y02D10/14 ,  Y02D10/151

Abstract: Full bandwidth communication buses are disclosed. While primarily focused on the Serial Low-power Inter-chip Media Bus (SLIMbus) communication bus, the concepts of the present disclosure may be extended to other communication buses. Exemplary aspects of the present disclosure utilize a reserved segment distribution code and a segment length to define a Segment Interval that is better-sized relative to raw data bits. By fitting the segment interval to the size of the raw data bits, bandwidth utilization is maximized, resulting in faster effective data transfers. Completion of such efficient data transfers may allow the communication bus to spend more time in a low-power mode and thus, conserve power. Additionally, such efficient data transfers may allow for better quality in presentation of multimedia content to the user.

公开(公告)号：US10073137B2

公开(公告)日：2018-09-11

申请号：US15226482

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Oren Reiss ,  Lior Amarilio ,  Amit Gil ,  Boaz Moskovich

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/2884 ,  G01R31/31705 ,  G01R31/3177 ,  G06F11/3656

Abstract: SoundWire-based embedded debugging in an electronic system is provided. In this regard, in one aspect, a SoundWire slave circuit receives a SoundWire data input signal over a SoundWire bus including two physical wires. The SoundWire data input signal includes a plurality of debug configuration bits in assigned SoundWire bitslots. The SoundWire slave circuit generates a plurality debug input bits required for debugging the SoundWire slave circuit based on the debug configuration bits received in the assigned SoundWire bitslots. In another aspect, the SoundWire slave circuit returns a SoundWire data output signal, which includes a debug output bit in an assigned SoundWire bitslot, over the SoundWire bus. By receiving debugging configurations and returning debugging results over the SoundWire bus, it is possible to debug the SoundWire slave circuit with a reduced number of physical pins, thus helping to reduce the overall pin count and footprint of the electronic device.

公开(公告)号：US20180038908A1

公开(公告)日：2018-02-08

申请号：US15226482

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Oren Reiss ,  Lior Amarilio ,  Amit Gil ,  Boaz Moskovich

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/2884 ,  G01R31/31705 ,  G01R31/3177 ,  G06F11/3656

Abstract: SoundWire-based embedded debugging in an electronic system is provided. In this regard, in one aspect, a SoundWire slave circuit receives a SoundWire data input signal over a SoundWire bus including two physical wires. The SoundWire data input signal includes a plurality of debug configuration bits in assigned SoundWire bitslots. The SoundWire slave circuit generates a plurality debug input bits required for debugging the SoundWire slave circuit based on the debug configuration bits received in the assigned SoundWire bitslots. In another aspect, the SoundWire slave circuit returns a SoundWire data output signal, which includes a debug output bit in an assigned SoundWire bitslot, over the SoundWire bus. By receiving debugging configurations and returning debugging results over the SoundWire bus, it is possible to debug the SoundWire slave circuit with a reduced number of physical pins, thus helping to reduce the overall pin count and footprint of the electronic device.

公开(公告)号：US20170168968A1

公开(公告)日：2017-06-15

申请号：US14969315

申请日：2015-12-15

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Boaz Moskovich

IPC: G06F13/24 ,  G06F13/42 ,  G06F13/364

CPC classification number: G06F13/24 ,  G06F13/364 ,  G06F13/4282

Abstract: Audio bus interrupts are disclosed. In one aspect, a new command (referred to herein as a Slave Interrupt Status command) is provided using a reserved Opcode within the SOUNDWIRE protocol. In response to a Ping Request by a slave, a master generates a PING command. The slave that generated the Ping Request sets a bit in a Ping Response according to the existing SOUNDWIRE protocol. However, instead of iteratively reading from each slave, the master uses the Slave Interrupt Status command to interrogate the requesting slave more thoroughly. In response to the Slave Interrupt Status command, the slave provides a more robust response that indicates interrupt requesting status of all registers within the slave that could generate an interrupt. Thus, the master is provided a complete list of which registers generate the original Ping Request and can act accordingly to address issues that generate the interrupt.