公开(公告)号：US20240153879A1

公开(公告)日：2024-05-09

申请号：US18367615

申请日：2023-09-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHING-YIH SHIH

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/80 ,  H01L25/105 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/08235 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/3512 ,  H01L2924/37001

Abstract: The semiconductor device includes a first die; a first redistribution structure positioned on the first die; a second die positioned on the first redistribution structure and including a first cache unit; and a third die positioned on the first redistribution structure, separated from the second die, and including a second cache unit. The first redistribution structure includes: a plurality of conductive layers electrically coupled the first die and the first cache unit and electrically coupled the first die and the second cache unit, respectively and correspondingly; and a bridge layer electrically isolated from the plurality of conductive layers, electrically connected the second die and the third die. The first cache unit and the second cache unit are topographically aligned with the first die. The first die is configured as a cache memory, and the second die and the third die are configured as logic dies.

公开(公告)号：US20240014048A1

公开(公告)日：2024-01-11

申请号：US17857752

申请日：2022-07-05

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHING-YIH SHIH

IPC: H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/373 ,  H01L23/367

CPC classification number: H01L21/4882 ,  H01L24/08 ,  H01L25/0657 ,  H01L24/80 ,  H01L23/3733 ,  H01L23/3677 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2225/06544 ,  H01L2924/35121 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method of manufacturing a semiconductor structure is provided. The method includes forming a thermal conductive structure embedded within a first passivation layer of a first wafer, and forming a plurality of conductive vias penetrating a first substrate of the first wafer and in contact with the thermal conductive structure. The method further includes forming a first connecting structure in contact with the thermal conductive structure and exposed by a surface of the first passivation layer. The method further includes bonding the first connecting structure of the first wafer to a second connecting structure of a second wafer, and bonding the first passivation layer of the first wafer to a first dielectric layer of the second wafer, wherein a first seal ring embedded within the first dielectric layer of the second wafer is thermally connected to the thermal conductive structure through the first connecting structure and the second connecting structure.

公开(公告)号：US20230386968A1

公开(公告)日：2023-11-30

申请号：US17751941

申请日：2022-05-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHING-YIH SHIH

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L23/562

Abstract: The present application provides a semiconductor structure having an elastic member within a via. The semiconductor structure includes a wafer including a substrate, a dielectric layer under the substrate, and a conductive pad surrounded by the dielectric layer; a passivation layer disposed over the substrate; a conductive via extending from the conductive pad through the substrate and the passivation layer and partially through the dielectric layer; and an elastic member disposed within the conductive via.

公开(公告)号：US20230386909A1

公开(公告)日：2023-11-30

申请号：US17752642

申请日：2022-05-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHING-YIH SHIH

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76831 ,  H01L24/80 ,  H01L24/03 ,  H01L21/76816 ,  H01L21/76898 ,  H01L2224/80895 ,  H01L24/08 ,  H01L2224/08146 ,  H01L24/05 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05082 ,  H01L2224/0391 ,  H01L21/76843 ,  H01L21/76819 ,  H01L21/7684

Abstract: A method of manufacturing a semiconductor structure includes: providing a first wafer including a first substrate, a first dielectric layer under the first substrate, and a first conductive pad surrounded by the first dielectric layer; disposing a first passivation layer over the first substrate; removing portions of the first dielectric layer, the first substrate and the first passivation layer to form a first opening exposing a portion of the first conductive pad; disposing a first conductive material within the first opening; disposing a first elastic material within the first opening and surrounded by the first conductive material; removing portions of the first conductive material and the first elastic material adjacent to an end of the first opening to form a first elastic member; and disposing a second conductive material over the first elastic member and the first conductive material to form a first conductive via surrounding the first elastic member.

公开(公告)号：US20230369264A1

公开(公告)日：2023-11-16

申请号：US17742544

申请日：2022-05-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHING-YIH SHIH ,  CHIH-CHING LIN

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L24/08 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/535 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80896

Abstract: The present application provides a semiconductor structure having vias with different dimensions and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; a second wafer including a second dielectric layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer; a passivation disposed over the second substrate; a first conductive via extending from the first conductive pad through the second wafer and the passivation, and having a first width surrounded by the second wafer; and a second conductive via extending from the second conductive pad through the passivation and the second substrate and partially through the second dielectric layer, and having a second width surrounded by the second wafer.

公开(公告)号：US20230369210A1

公开(公告)日：2023-11-16

申请号：US17742959

申请日：2022-05-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHING-YIH SHIH ,  CHIH-CHING LIN

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/7688 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226

Abstract: The present application provides a method of manufacturing a semiconductor structure having vias with different dimensions and a manufacturing method of the semiconductor structure. The method includes: providing a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; providing a second wafer including a second dielectric layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer; forming a passivation over the second substrate; forming a first conductive via extending from the first conductive pad through the second wafer and the passivation, and having a first width surrounded by the second wafer; and forming a second conductive via extending from the second conductive pad through the passivation and the second substrate and partially through the second dielectric layer, and having a second width surrounded by the second wafer.

公开(公告)号：US20230178494A1

公开(公告)日：2023-06-08

申请号：US17541772

申请日：2021-12-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHING-YIH SHIH

IPC: H01L23/544 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/544 ,  H01L23/5226 ,  H01L21/76802 ,  H01L2223/54426

Abstract: The present application discloses a semiconductor device having integral alignment marks with decoupling features and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a dielectric stack positioned on the substrate; two conductive features positioned in the dielectric stack; a decoupling unit positioned in the dielectric stack, between the two second conductive features, and comprising a bottle-shaped cross-sectional profile; and an alignment mark positioned on the decoupling unit. The alignment mark comprises a fluorescence material.

公开(公告)号：US20230113020A1

公开(公告)日：2023-04-13

申请号：US17500026

申请日：2021-10-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHING-YIH SHIH

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/29

Abstract: The present application discloses a semiconductor device with a re-fill layer. The semiconductor device includes a chip stack including a first base die; a first stacked die positioned on a front surface of the first base die; and a re-fill layer positioned on a sidewall of the stacked die. The re-fill layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, titanium oxide, aluminum oxide, or hafnium oxide.

公开(公告)号：US20220077068A1

公开(公告)日：2022-03-10

申请号：US17529507

申请日：2021-11-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHING-YIH SHIH

IPC: H01L23/538 ,  H01L21/768

Abstract: A method of manufacturing a semiconductor structure includes steps of providing a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; providing a second wafer including a second substrate, a second dielectric layer over the second substrate, and a second conductive pad surrounded by the second dielectric layer; bonding the first dielectric layer with the second dielectric layer; forming a first opening extending through the second substrate and partially through the second dielectric layer; disposing a dielectric liner conformal to the first opening; forming a second opening extending through the second dielectric layer and the second conductive pad to at least partially expose the first conductive pad; and disposing a conductive material within the first opening and the second opening to form a conductive via over the first conductive pad.

公开(公告)号：US20220077056A1

公开(公告)日：2022-03-10

申请号：US17529487

申请日：2021-11-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHING-YIH SHIH

IPC: H01L23/522 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L23/29

Abstract: A semiconductor device includes a conductive pattern formed over a semiconductor substrate, and an interconnect structure formed over the conductive pattern. The semiconductor device also includes a first passivation layer over the conductive pattern; a second passivation layer over the first passivation layer; an interconnect structure disposed over the conductive pattern and in the first passivation layer and the second passivation layer; and an interconnect liner disposed between the interconnect structure and the conductive pattern and surrounding the interconnect structure, wherein inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern