公开(公告)号：US06597630B1

公开(公告)日：2003-07-22

申请号：US10253883

申请日：2002-09-25

Applicant: Takashi Kubo ,  Yasuhiro Konishi ,  Takashi Kono

Inventor： Takashi Kubo ,  Yasuhiro Konishi ,  Takashi Kono

IPC: G11C700

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072

Abstract: There are provided a control signal generation circuit receiving an external instruction input in synchronization with a clock signal to generate a control signal for defining a data output period in response to the external instruction, and an output buffer circuit receiving data read from a memory array for output to an output node for the data output period, and there is further provided an output control circuit for controlling turning first, second and third transistors on and off, the output control circuit in the data out period turning on and off one of the first and second transistors complementarily in response to the read data and also turning on the third transistor in response to the control signal.

Abstract translation: 提供了一个与时钟信号同步地接收外部指令输入的控制信号发生电路，以产生用于响应于外部指令定义数据输出周期的控制信号，以及一个从存储器阵列读取的数据的输出缓冲电路， 输出到用于数据输出周期的输出节点，并且还提供一个输出控制电路，用于控制第一，第二和第三晶体管的导通和截止，输出控制电路在数据输出周期内接通和关断第一， 和第二晶体管互补地响应于读取的数据，并且还响应于控制信号接通第三晶体管。

公开(公告)号：US06489819B1

公开(公告)日：2002-12-03

申请号：US09179411

申请日：1998-10-27

Applicant: Takashi Kono ,  Takeshi Hamamoto ,  Yasuhiro Konishi

Inventor： Takashi Kono ,  Takeshi Hamamoto ,  Yasuhiro Konishi

IPC: G11C700

CPC classification number: G11C29/14

Abstract: Pulses are generated using an edge of a clock signal applied from a low speed tester as a trigger, and internal clock signals are generated utilizing the pulses. Internal circuitry is operated in synchronization with the internal clock signals. Thus a synchronous semiconductor device operating at high speed can be tested using a low speed tester.

Abstract translation: 使用从低速测试仪施加的时钟信号的边沿作为触发产生脉冲，并且使用脉冲产生内部时钟信号。 内部电路与内部时钟信号同步工作。 因此，可以使用低速测试仪来测试以高速操作的同步半导体器件。

公开(公告)号：US06170036A

公开(公告)日：2001-01-02

申请号：US08780066

申请日：1996-12-23

Applicant: Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

Inventor： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

IPC: G06F1300

CPC classification number: G11C7/1006 ,  G06F12/0893 ,  G11C7/103 ,  G11C7/1045 ,  G11C11/005 ,  G11C2207/2254

Abstract: A semiconductor memory device is configured to include a static random access memory (SRAM) array and a dynamic random access memory (DRAM) array. The memory device includes an internal data line which enables the transfer of data blocks between the SRAM and DRAM arrays. Data transfer circuitry is provided separately from the internal data line and includes a latch circuit for latching the data to be transferred. The data transfer circuitry is responsive to a transfer designating signal.

Abstract translation: 半导体存储器件被配置为包括静态随机存取存储器（SRAM）阵列和动态随机存取存储器（DRAM）阵列。 存储器件包括内部数据线，其能够在SRAM和DRAM阵列之间传输数据块。 数据传输电路与内部数据线分开提供，并且包括用于锁存要传送的数据的锁存电路。 数据传输电路响应传输指定信号。

公开(公告)号：US6157992A

公开(公告)日：2000-12-05

申请号：US768089

申请日：1996-12-16

Applicant: Seiji Sawada ,  Yasuhiro Konishi

Inventor： Seiji Sawada ,  Yasuhiro Konishi

IPC: G11C11/407 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G06F12/00

CPC classification number: G11C7/1072

Abstract: A read enable signal OEMF activated in response to an input command is applied to an N minus 2 clock shift circuit included in an output control circuit for implementation of ZCAS latency. An output signal of the N minus 2 clock shift circuit and an internal mask instructing signal activated in response to an external mask instructing signal are logically processed and applied to a one-clock shift circuit. According to an output signal OEMQM of one-clock shift circuit, a data output enable signal OEM controlling activation/inactivation of an output buffer circuit is activated/inactivated. Data output controlling portion occupying area of a synchronous dynamic random access memory is reduced and timings of activation/inactivation of data output by different commands are made the same.

Abstract translation: 响应于输入命令而激活的读使能信号OEMF被施加到包括在用于实现ZCAS延迟的输出控制电路中的N-2时钟移位电路。 N减2时钟移位电路的输出信号和响应于外部掩码指示信号而被激活的内部掩码指示信号被逻辑地处理并施加到一个时钟的移位电路。 根据一时钟移位电路的输出信号OEMQM，激活/禁止输出缓冲电路的数据输出使能信号OEM控制激活/失活。 同步动态随机存取存储器的数据输出控制部占用面积减少，不同命令输出的数据的激活/失活定时相同。

公开(公告)号：US6026029A

公开(公告)日：2000-02-15

申请号：US865310

申请日：1997-05-29

Applicant: Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

Inventor： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC: G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC classification number: G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5946266A

公开(公告)日：1999-08-31

申请号：US946650

申请日：1997-10-07

Applicant: Hisashi Iwamoto ,  Yasuhiro Konishi

Inventor： Hisashi Iwamoto ,  Yasuhiro Konishi

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/409 ,  G11C8/00

CPC classification number: G11C7/1072 ,  G11C7/22

Abstract: In a synchronous dynamic random access memory (SDRAM), one bank A is divided into banks A0 and A1, and two sets of writing-related circuits are arranged corresponding to each memory cell array bank and are capable of performing writing operation substantially independently. The first and second bits of write data applied successively from the outside world are applied alternately to write registers. Since the I/O line pair is connected to the selected memory cells in respective memory cell array banks after incorporation of the second bit data to be written is completed, the potential levels of the corresponding I/O line pair always change to the corresponding potential levels from the initial state in writing the first and second bit data.

Abstract translation: 在同步动态随机存取存储器（SDRAM）中，一组A分为存储体A0和A1，并且对应于每个存储单元阵列组布置两组写相关电路，并且能够基本上独立地执行写操作。 从外部连续应用的写入数据的第一和第二位被交替地应用于写入寄存器。 由于在结合待写入的第二位数据结束之后I / O线对连接到相应存储单元阵列组中的所选存储单元，所以相应I / O线对的电位电平总是变为相应的电位 从初始状态写入第一和第二位数据的电平。

公开(公告)号：US5867446A

公开(公告)日：1999-02-02

申请号：US332626

申请日：1994-10-31

Applicant: Yasuhiro Konishi ,  Takayuki Miyamoto ,  Takeshi Kajimoto ,  Hisashi Iwamoto

Inventor： Yasuhiro Konishi ,  Takayuki Miyamoto ,  Takeshi Kajimoto ,  Hisashi Iwamoto

IPC: G11C7/10 ,  G11C8/12 ,  G11C8/00

CPC classification number: G11C7/1072 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12

Abstract: Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.

公开(公告)号：US5848004A

公开(公告)日：1998-12-08

申请号：US625578

申请日：1996-03-28

Applicant: Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

Inventor： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC: G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC classification number: G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5603009A

公开(公告)日：1997-02-11

申请号：US356046

申请日：1994-12-14

Applicant: Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

Inventor： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

IPC: G06F12/08 ,  G11C7/10 ,  G11C11/00 ,  G06F13/00 ,  G11C11/34

CPC classification number: G11C7/1006 ,  G06F12/0893 ,  G11C11/005 ,  G11C7/103 ,  G11C7/1045 ,  G11C2207/2254

Abstract: A semiconductor memory device containing a cache includes a static random access memory (SRAM) as a cache memory, and a dynamic random access memory (DRAM) as a main memory. Collective transfer of data blocks is possible between the DRAM and the SRAM through a bi-directional data transfer gate circuit and through an internal data line. A DRAM row decoder and a DRAM column decoder are provided in the DRAM. A SRAM row decoder and an SRAM column decoder are provided in the SRAM. Addresses of the SRAM and DRAM can be independently applied. The data transfer gate includes a latch circuit for latching data from the SRAM, which serves as a high speed memory, an amplifier circuit and a gate circuit for amplifying data from the DRAM, which serves as a large capacity memory, and for transmitting the amplified data to the SRAM, and a gate circuit, responsive to a DRAM write enable signal for transmitting write data to corresponding memory cells of the DRAM. After the data of the SRAM has been latched by a latch circuit, write data is transmitted from the gate circuit to the DRAM, and the write data is transmitted to the SRAM through the amplifier circuit and the gate circuit.

Abstract translation: 包含高速缓存的半导体存储器件包括作为高速缓冲存储器的静态随机存取存储器（SRAM）和作为主存储器的动态随机存取存储器（DRAM）。 通过双向数据传输门电路和内部数据线，可以在DRAM和SRAM之间进行数据块的集中传输。 在DRAM中提供DRAM行解码器和DRAM列解码器。 在SRAM中提供SRAM行解码器和SRAM列解码器。 SRAM和DRAM的地址可以独立应用。 数据传输门包括一个锁存电路，用于锁存来自用作高速存储器的SRAM的数据，放大器电路和用于放大来自DRAM的数据的门电路，其用作大容量存储器，并用于发送放大 数据到SRAM，以及门电路，响应于用于将写入数据发送到DRAM的相应存储器单元的DRAM写使能信号。 在SRAM的数据被锁存电路锁存之后，写入数据从门电路传输到DRAM，写数据通过放大电路和门电路传输到SRAM。

公开(公告)号：US5594704A

公开(公告)日：1997-01-14

申请号：US419566

申请日：1995-04-10

Applicant: Yasuhiro Konishi ,  Takayuki Miyamoto ,  Takeshi Kajimoto ,  Hisashi Iwamoto

Inventor： Yasuhiro Konishi ,  Takayuki Miyamoto ,  Takeshi Kajimoto ,  Hisashi Iwamoto

IPC: G11C7/10 ,  G11C8/12 ,  G11C8/00

CPC classification number: G11C8/12 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1072

Abstract: Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.

Abstract translation: 存储器阵列被分成可以相互独立操作的存储体。 为银行提供读取数据存储寄存器和彼此独立操作的写入数据存储寄存器。 存储器阵列被分成多个小阵列块，对应于每个阵列块布置本地IO线，并且本地IO线连接到全局IO线。 全局IO线连接到前置放大器组并写入缓冲组。 通过控制信号发生电路和寄存器控制电路，可以仅在连续写入操作期间禁止写入期望的位，如果数据写入应该是数据写入时，可以将数据集中写入所选择的存储器单元 在连续写入之前到达卷绕长度之前停止，并且可以延迟在重复执行写入周期时激活存储器阵列的定时。 提供了具有小芯片面积，高运行速度，低功耗和多种功能的同步半导体存储器件。