公开(公告)号：US20220245753A1

公开(公告)日：2022-08-04

申请号：US17720804

申请日：2022-04-14

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06F7/483 ,  G06N3/08 ,  G06F9/30 ,  G06N3/04 ,  G06N3/063 ,  G06F9/50 ,  G06F9/38 ,  G06N20/00

Abstract: Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple or mixed precisions and dynamic ranges.

公开(公告)号：US11379235B2

公开(公告)日：2022-07-05

申请号：US17128972

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Feng Chen ,  Narayan Srinivasa ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Joydeep Ray ,  Nicolas C. Galoppo Von Borries ,  Prasoonkumar Surti ,  Ben J. Ashbaugh ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan

IPC: G06T15/00 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0862 ,  G06F9/50 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063

Abstract: A mechanism is described for facilitating intelligent dispatching and vectorizing at autonomous machines. A method of embodiments, as described herein, includes detecting a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a graphics processor. The method may further include determining a first set of threads of the plurality of threads that are similar to each other or have adjacent surfaces, and physically clustering the first set of threads close together using a first set of adjacent compute blocks.

公开(公告)号：US20220197715A1

公开(公告)日：2022-06-23

申请号：US17693010

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Ben J. Ashbaugh ,  Michael Kinsner ,  James Brodman ,  Rajesh Poornachandran

IPC: G06F9/50

Abstract: An apparatus to facilitate data parallel programming-based transparent transfer across heterogeneous devices is disclosed. The apparatus includes a processor to: identify a change in device status that triggers a device transfer process from an original device, wherein the original device is associated with a queue of an application program of a data parallel programming runtime; identify a new device that is compatible with the original device; migrate at least one of a state or data of the original device to the new device; logically map, without user intervention, the queue to the new device in the data parallel programming runtime; and initiate execution of the application program on the new device using the queue.

公开(公告)号：US20220197615A1

公开(公告)日：2022-06-23

申请号：US17692425

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Michael Kinsner ,  Ben J. Ashbaugh ,  James Brodman ,  Rajesh Poornachandran

IPC: G06F8/41 ,  G06F9/48

Abstract: An apparatus to facilitate data parallel programming task graph optimization through device telemetry is disclosed. The apparatus includes a processor to: receive, from a compiler, compiled code generated from source code of an application, the compiled code to support a workload of the application; generate a task graph of the application using the compiled code, the task graph to represent at least one of a relationship or dependency of the compiled code; receive runtime telemetry data corresponding to execution of the compiled code on the one or more accelerator devices; identify one or more scheduling optimizations for the one or more accelerator devices based on the task graph and the received telemetry data; and provide a scheduling command to cause the one or more scheduling optimizations to be implemented in the one or more accelerator devices.

公开(公告)号：US20220197610A1

公开(公告)日：2022-06-23

申请号：US17692413

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Michael Kinsner ,  John Freeman ,  Ben J. Ashbaugh ,  Rajesh Poornachandran

IPC: G06F8/41 ,  G06F9/54

Abstract: An apparatus to facilitate incremental just-in-time (JIT) performance refinement for programmable logic device offload is disclosed. The apparatus includes a processor to: initiate multiple just-in-time (JIT) compilation iterations of an application; program a first architecture of a first compilation of the multiple JIT compilation iterations to a programmable logic device and execute the application on the first architecture, wherein the first compilation comprises a faster compilation time amongst the multiple JIT compilation iterations; identify a hotspot; determine that a second compilation of the multiple JIT compilation iterations is complete, wherein the second compilation comprises a slower compilation time than the first compilation; and program a second architecture of the second compilation of the multiple JIT compilation iterations to the programmable logic device and execute the application on the second architecture.

公开(公告)号：US11308574B2

公开(公告)日：2022-04-19

申请号：US16983080

申请日：2020-08-03

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06F7/483 ,  G06N3/08 ,  G06F9/30 ,  G06N3/04 ,  G06N3/063 ,  G06F9/50 ,  G06F9/38 ,  G06N20/00 ,  G06F3/14 ,  G06T1/60 ,  G06T15/00

Abstract: Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple precisions.

公开(公告)号：US11217040B2

公开(公告)日：2022-01-04

申请号：US16383849

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： Barath Lakshamanan ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Elmoustapha Ould-Ahmed-Vall ,  Liwei Ma ,  Jingyi Jin ,  Justin E. Gottschlich ,  Chandrasekaran Sakthivel ,  Michael S. Strickland ,  Brian T. Lewis ,  Lindsey Kuper ,  Altug Koker ,  Abhishek R. Appu ,  Prasoonkumar Surti ,  Joydeep Ray ,  Balaji Vembu ,  Javier S. Turek ,  Naila Farooqui

IPC: G05D1/00 ,  G07C5/00 ,  G08G1/01 ,  H04W28/08 ,  H04L29/08 ,  G06N20/00 ,  G06F9/50 ,  G01C21/34 ,  B60W30/00 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N20/10 ,  G08G1/052 ,  G01S19/13 ,  H04L12/26 ,  G05D1/02

Abstract: One embodiment provides for a computing device within an autonomous vehicle, the compute device comprising a wireless network device to enable a wireless data connection with an autonomous vehicle network, a set of multiple processors including a general-purpose processor and a general-purpose graphics processor, the set of multiple processors to execute a compute manager to manage execution of compute workloads associated with the autonomous vehicle, the compute workload associated with autonomous operations of the autonomous vehicle, and offload logic configured to execute on the set of multiple processors, the offload logic to determine to offload one or more of the compute workloads to one or more autonomous vehicles within range of the wireless network device.

公开(公告)号：US10776897B1

公开(公告)日：2020-09-15

申请号：US16297129

申请日：2019-03-08

Applicant: Intel Corporation

Inventor： James Valerio ,  Vasanth Ranganathan ,  Joydeep Ray ,  Abhishek R. Appu ,  Ben J. Ashbaugh ,  Brandon Fliflet ,  Jeffery S. Boles ,  Srinivasan Embar Raghukrishnan ,  Rahul Kulkarni

IPC: G06T1/20 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a processor to configure a plurality of contexts of a command engine to execute a graphics workload comprising a plurality of walkers, allocate, from a pool of execution units of a graphics processor, a subset of execution units to each walker in the plurality of walkers based at least in part on the predetermined number of walkers configured for the context, for each context in the plurality of contexts, dispatch one or more walkers of the plurality of walkers to the execution units, and upon dispatch of the one or more walkers of the plurality of walkers, write an opcode to a computer-readable memory indicating that the dispatch of the walker is complete, wherein the opcode comprises dependency data for the one or more walkers of the plurality of walkers. Other embodiments may be described and claimed.

公开(公告)号：US10521349B2

公开(公告)日：2019-12-31

申请号：US16277267

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Prasoonkumar Surti ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Abhishek R. Appu ,  Nicolas C. Galoppo Von Borries ,  Joydeep Ray ,  Narayan Srinivasa ,  Feng Chen ,  Ben J. Ashbaugh ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/0837 ,  G06N3/08 ,  G06N20/00 ,  G06T1/20 ,  G06F12/0815 ,  G06N3/04 ,  G06N3/063

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

公开(公告)号：US10332320B2

公开(公告)日：2019-06-25

申请号：US15488914

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Barath Lakshamanan ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Elmoustapha Ould-Ahmed-Vall ,  Liwei Ma ,  Jingyi Jin ,  Justin E. Gottschlich ,  Chandrasekaran Sakthivel ,  Michael S. Strickland ,  Brian T. Lewis ,  Lindsey Kuper ,  Altug Koker ,  Abhishek R. Appu ,  Prasoonkumar Surti ,  Joydeep Ray ,  Balaji Vembu ,  Javier S. Turek ,  Naila Farooqui

IPC: G01C22/00 ,  G07C5/00 ,  G05D1/00 ,  G01C21/34 ,  G08G1/01 ,  H04W28/08 ,  G06N20/00 ,  G06F9/50 ,  G08G1/052 ,  G01S19/13 ,  G05D1/02 ,  H04L29/08 ,  H04L12/26

Abstract: One embodiment provides for a computing device within an autonomous vehicle, the compute device comprising a wireless network device to enable a wireless data connection with an autonomous vehicle network, a set of multiple processors including a general-purpose processor and a general-purpose graphics processor, the set of multiple processors to execute a compute manager to manage execution of compute workloads associated with the autonomous vehicle, the compute workload associated with autonomous operations of the autonomous vehicle, and offload logic configured to execute on the set of multiple processors, the offload logic to determine to offload one or more of the compute workloads to one or more autonomous vehicles within range of the wireless network device.