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    ENCODER AND OPERATION METHOD THEREOF
    42.
    发明申请
    ENCODER AND OPERATION METHOD THEREOF 有权

    公开(公告)号：US20230125421A1

    公开(公告)日：2023-04-27

    申请号：US17893815

    申请日：2022-08-23

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Tae Wook KANG ,  Sung Eun KIM ,  Kyung Jin BYUN ,  Kwang IL OH ,  Jae-Jin LEE

    IPC: G06N3/04 ,  G06N10/20

    Abstract: Disclosed is operation method of an encoder that receives a continuous time-series signal and respectively transmits first to N-th input signals to first to N-th input neuron circuits of spike neural network circuit. The method of operating the encoder includes receiving the continuous time-series signal, generating a plurality of discrete quantum signals by sampling and quantizing the continuous time-series signal, selecting first to N-th discrete quantum signals among the plurality of discrete quantum signals, matching the selected first to N-th discrete quantum signals with the first to N-th input neuron circuits, respectively, identifying discrete quantum signals, each of which has a quantum level different from a quantum level of a previous discrete quantum signal, from among the second to N-th discrete quantum signals, and activating the input signals to be transmitted to the input neuron circuits corresponding to the identified discrete quantum signals and the first discrete quantum signal.

    LOW POWER SYSTEM ON CHIP
    43.
    发明申请
    LOW POWER SYSTEM ON CHIP 有权

    公开(公告)号：US20220413544A1

    公开(公告)日：2022-12-29

    申请号：US17847636

    申请日：2022-06-23

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kyuseung HAN ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Hyung-IL PARK ,  Kwang IL OH ,  Jae-Jin LEE

    IPC: G06F1/10 ,  G06F15/78

    Abstract: A low power system on chip for supporting partial clock gating is provided. The system on chip includes a network on chip including a first CG-network interface module, a second CG-network interface module, and a clock gating control module, a first IP block that communicates through the first CG-network interface module, and a second IP block that communicates through the second CG-network interface module. The clock gating control module receives a clock gating request from the first IP block, outputs a communication control signal to the second CG-network interface module in response to the received clock gating request, and performs a clock gating operation for a clock signal in response to the received clock gating request to selectively deliver the clock signal to the second IP block.

    SPIKING NEURAL NETWORK CIRCUIT
    46.
    发明申请
    SPIKING NEURAL NETWORK CIRCUIT 有权

    公开(公告)号：US20220156556A1

    公开(公告)日：2022-05-19

    申请号：US17446685

    申请日：2021-09-01

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kwang IL OH ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Hyung-IL PARK ,  Jae-Jin LEE

    IPC: G06N3/04 ,  G06N3/063 ,  H03K19/20

    Abstract: Disclosed is a spiking neural network circuit, which includes an axon circuit that generates an input spike signal, a first synapse zone and a second synapse zone each including one or more synapses, wherein each of the synapses is configured to perform an operation based on the input spike signal and each weight, and a neuron circuit that generates an output spike signal based on operation results of the synapses. The input spike signal is transferred to the first synapse zone and the second synapse zone through a tree structure, and each of branch nodes of the tree structure includes a driving buffer.

    ELECTRONIC CIRCUIT FOR ADJUSTING PHASE OF CLOCK
    48.
    发明申请
    ELECTRONIC CIRCUIT FOR ADJUSTING PHASE OF CLOCK 审中-公开

    公开(公告)号：US20200067516A1

    公开(公告)日：2020-02-27

    申请号：US16542469

    申请日：2019-08-16

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： KWANG IL OH ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Mi Jeong PARK ,  Hyung-IL PARK ,  Kyung Jin BYUN ,  Jae-Jin LEE ,  In Gi LIM

    IPC: H03L7/093

    Abstract: The inventive concept includes an oscillating circuit, a phase inverting circuit, and a phase detecting circuit. The oscillating circuit generates a first clock to be used to sample an input signal. The phase inverting circuit outputs a second clock based on the first clock. The phase detecting circuit generates a control signal having a first logic value when a phase difference between a phase of the input signal and a phase of the second clock is less than a reference value for a reference time or more. The phase detecting circuit generates the control signal having a second logic value when the phase difference is equal to or greater than the reference value or when the phase difference is less than the reference value for a time shorter than the reference time. The phase inverting circuit inverts the phase of the second clock when a logic value of the control signal changes from the first logic value to the second logic value or when a logic value of the control signal changes from the second logic value to the first logic value.

    SEMICONDUCTOR DEVICE INCLUDING CMOS CIRCUIT AND OPERATION METHOD THEREOF
    49.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING CMOS CIRCUIT AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20190245532A1

    公开(公告)日：2019-08-08

    申请号：US16262738

    申请日：2019-01-30

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Tae Wook KANG ,  Jae-Jin LEE ,  Kwang IL OH ,  Sung Eun KIM ,  Sukho LEE ,  Kyuseung HAN

    IPC: H03K17/14 ,  H03K17/08

    CPC classification number: H03K17/145 ,  H03K17/08 ,  H03K2017/0806 ,  H03K2217/0027

    Abstract: The inventive concept relates to a semiconductor device including a CMOS circuit and an operation method thereof. A semiconductor device according to an embodiment of the inventive concept includes a semiconductor circuit, a controller, and a voltage generator. The semiconductor circuit operates at a drive voltage to reduce the delay time between input and output as the temperature increases. The controller determines the malfunction of the CMOS circuit based on the difference between the source-drain current of the PMOS transistor and the source-drain current of the NMOS transistor as the temperature changes. The voltage generator generates or adjusts a body-bias voltage applied to the PMOS transistor or the NMOS transistor based on a malfunction determination of the controller. According to the inventive concept, malfunctions and performance deterioration occurring in a CMOS circuit operating at a low voltage may be reduced.

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